I have problem with LVDS TX PLL lock for some resolutions (frequencies)!
I use two pixel per clock output format (odd and even pixel simultaneously with half clock rate).
Input (HDMI part) is locked ok with correct clock frequency and resolution, but LVDS TX PLL failed to lock.
I notice that PLL GEAR setting is not consistent in manual (UG907) and script ver1.1c:
ug907;
• From 25 MHz to 40 MHz: TX_PLL_GEAR[2:0] must be set to 000.
• From 40 MHz to 92 MHz: TX_PLL_GEAR[2:0] must be set to 010.
Here manual also mention frequency 200 MHz as boundary:
TX_PLL_GEAR[2:0] Description
000 0 to 200 MHz (default)
010 200 MHz to 300 MHz
From where 200MHz come from? LVDS is 7:1 serializer, but 40MHz*7 is 280MHz != 200MHz ??
script:
mention 27MHz as boundary - here I am not sure is that HDMI TMDS frequency or already half of frequency because of two pixel per clock mode for output LVDS transmitter!
I made fee experiments and I found that for example if I have LVDS TX frequency of 42MHz (84MHz HDMI frequency), LVDS TX PLL will lock with GEAR setting 000 and it will not lock with 010.(UG907 suggest 010)
Q:
How to adjust PLL GEAR setting?
Is there some sequence that I must follow? (for example wait for HDMI input lock and then release LVDS TX PLL)
Is there LVDS TX PLL release sequence?
Thanks in advance,
Br,
Eugen
