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ADV7613 LVDS transmitter TX_PLL_GEAR settings

I have problem with LVDS TX PLL lock for some resolutions (frequencies)!

I use two pixel per clock output format (odd and even pixel simultaneously with half clock rate).

Input (HDMI part) is locked ok with correct clock frequency and resolution, but LVDS TX PLL failed to lock.

I notice that PLL GEAR setting is not consistent in manual (UG907) and script ver1.1c: 


• From 25 MHz to 40 MHz: TX_PLL_GEAR[2:0] must be set to 000.
• From 40 MHz to 92 MHz: TX_PLL_GEAR[2:0] must be set to 010.

Here manual also mention frequency 200 MHz as boundary:

TX_PLL_GEAR[2:0]    Description
000                              0 to 200 MHz (default)
010                              200 MHz to 300 MHz

From where 200MHz come from? LVDS is 7:1 serializer, but 40MHz*7  is 280MHz != 200MHz ??


mention 27MHz as boundary - here I am not sure is that HDMI TMDS frequency or already half of frequency because of two pixel per clock mode for output LVDS transmitter! 

I made fee experiments and I found that for example if I have LVDS TX frequency of 42MHz (84MHz HDMI frequency), LVDS TX PLL will lock with GEAR setting 000 and it will not lock with 010.(UG907 suggest 010)


How to adjust PLL GEAR setting?

Is there some sequence that I must follow? (for example wait for HDMI input lock and then release LVDS TX PLL)

Is there LVDS TX PLL release sequence?

Thanks in advance,




  • Hi,

    The designers expect the PLL lock time to be in the order of tens of milliseconds up to a couple of video frames.

    There is a gears and such that the PLLs can select in order to be in the correct lock/acquire range. All in all this process is expected to take only a few video frames at most.

    At 60Hz refresh that would be 16ms per video frame. So a wait time of 110ms is approx 6 video frames at a 60Hz refresh.

    Unless the input was of very bad quality (ie. jittery, bad signal integrity) then 110ms is seen by our designers as an ample time to wait to allow the PLL to lock under normal circumstances. Please refer here



  • Post (and earlier posts) that you send me are related to TMDS clock transition on HDMI TX (ADV7511W).

    How is that related to HDMI RX (ADV7613) and LVDS TX inside ADV7613?

    As HDMI source I use my PC.

    LOCK time is currently not an issue - I never got LOCK with PLL_GEAR settings that manual suggest!

    I have HDMI RX PLL lock, but not LVDS TX lock inside same chip (ADV7613).



  • Hi,

     Please make sure with below recommended writes configured for LVDS Output.ADI recommends the below register setting should be programmed to setup the ADV7613 in LVDS mode.

          C0 43 03 ADI Recommended write
          C0 45 04 ADI Recommended write
          C0 46 53 ADI Recommended write
          C0 47 03 ADI Recommended write

    And also configure 4c register as C0 4C 11(8-bit) ; default 0x71, Bit [6] tx_oldi_hs_pol - 1'b0 = HS Polarity Neg, Bit [5] tx_oldi_vs_pol - 1'b0 = VS Polarity Neg, Bit [4] tx_oldi_de_pol - 1'b1 =  DE Polarity Pos, Bit [3] tx_enable_ns_mapping - 1'b0 = normal oldi 8-bit mapping, Bit [2] tx_656_all_lanes_enable - 1'b0 = disable 656 data on lanes ,Bit [1] tx_oldi_balanced_mode - 1'b0 = Non DC balanced ,Bit [0] tx_color_mode - 1'b1 = 8-bit mode



  • Hi Poornima,

    Yes, I have all registers that you mention in my initialization.

    Here is my init.

    ADV7613IicInitT ADV7613_Init[] = {
        {0x98, 0xF4, 0x80}, // CEC I2C ADR.
        {0x98, 0xF5, 0x7C}, // INFOFRAME I2C ADR.
        {0x98, 0xF8, 0x4C}, // DPLL I2C ADR.
        {0x98, 0xF9, 0x64}, // KSV I2C ADR.
        {0x98, 0xFA, 0x6C}, // EDID I2C ADR.
        {0x98, 0xFB, 0x68}, // HDMI I2C ADR.
        {0x98, 0xFD, 0x44}, // CP I2C ADR.
        {0x98, 0xE9, 0xC0}, // LVDS I2C ADR.    
        {0x98, 0x00, 0x02}, // VIDEO STANDARD - SAMO VAZAN ZA FREE FUN MODE
    	{0x98, 0x01, 0x06}, // PRIMARY MODE - HDMI GRAPHICS
    	{0x98, 0x02, 0xF2},	  // HDMI color space, RGB out
    	{0x98, 0x03, 0x42},	  // format select: 36-bit, 4:4:4 SDR Mode 0
        {0x98, 0x04, 0x63},	  // odd-even alignment fix
        {0x98, 0x05, 0x20},  // odd-even alignment fix	 
        {0x44, 0xBA, 0x00}, // DISABLE FREE RUN
        {0x44, 0x8B, 0x40},  // odd-even alignment fix
        {0x44, 0x8C, 0x02},  // odd-even alignment fix
        {0x44, 0x8D, 0x02},  // odd-even alignment fix	 
        {0x98, 0x0C, 0x42}, // disable POWER_DOWN
        {0x98, 0x15, 0xAE}, // EG why enabling audio pins?	 
        {0x44, 0x6C, 0x00}, // ADI recommended write	 
        {0x64, 0x40, 0x81}, // BCAPS[7:0] - Disable HDCP 1.1 features (default 0x83)	 
        {0x68, 0x6C, 0x14}, // HPA SETTINGS
        {0x68, 0x03, 0x98}, // ADI recommended write
        {0x68, 0x10, 0xA5}, // ADI recommended write
        {0x68, 0x1B, 0x08}, // ADI recommended write
        {0x68, 0x45, 0x04}, // ADI recommended write
        {0x68, 0x97, 0xC0}, // ADI recommended write
        {0x68, 0x3D, 0x10}, // ADI recommended write
        {0x68, 0x3E, 0x7B}, // ADI recommended write
        {0x68, 0x3F, 0x5E}, // ADI recommended write
        {0x68, 0x4E, 0xFE}, // ADI recommended write
        {0x68, 0x4F, 0x08}, // ADI recommended write
        {0x68, 0x57, 0xA3}, // ADI recommended write
        {0x68, 0x58, 0x07}, // ADI recommended write
        {0x68, 0x6F, 0x08}, // ADI recommended write
        {0x68, 0x83, 0xFE}, // ADI recommended write
    	{0x68, 0x86, 0x9B}, // ADI recommended write
        {0x68, 0x85, 0x10}, // ADI recommended write - input clock > 40MHz  
        {0x68, 0x89, 0x01}, // ADI recommended write
        {0x68, 0x9B, 0x03}, // ADI recommended write
        {0x68, 0x9C, 0x80}, // ADI recommended write
        {0x68, 0x9C, 0xC0}, // ADI recommended write
        {0x68, 0x9C, 0x00}, // ADI recommended write
        {0xc0, 0x40, 0x08}, // ENABLE PLL
        {0xc0, 0x43, 0x03}, // ADI recommended write
        {0xC0, 0x44, 0x02}, // PLL FREQUENCY: 2: 200-300MHz, 0: 0-200MHz, From 40 MHz to 92 MHz: TX_PLL_GEAR[2:0] must be set to 2, From 25 MHz to 40 MHz: TX_PLL_GEAR[2:0] must be set to 0.
        {0xc0, 0x45, 0x04}, // ADI recommended write
        {0xc0, 0x46, 0x53}, // ADI recommended write
        {0xc0, 0x47, 0x03}, // ADI recommended write
        {0xc0, 0x4C, 0x11}, // 8BIT, DE ACTIVE HIGH; HS, VS - active low
        {0xc0, 0x4E, 0x04}  // enable 8-bit mode in openldi tx (undocumented)
    ADV7613IicInitT ADV7613_EDID_Init[] = {
    		{0x6C, 0x00, 0x00},
    		{0x6C, 0x01, 0xFF},
    		{0x6C, 0x02, 0xFF},
    		{0x6C, 0x03, 0xFF},
    		{0x6C, 0x04, 0xFF},
    		{0x6C, 0x05, 0xFF},
    		{0x6C, 0x06, 0xFF},
    		{0x6C, 0x07, 0x00},
    		{0x6C, 0x08, 0x63},
    		{0x6C, 0x09, 0x2C},
    		{0x6C, 0x0A, 0x02},
    		{0x6C, 0x0B, 0x50},
    		{0x6C, 0x0C, 0x00},
    		{0x6C, 0x0D, 0x00},
    		{0x6C, 0x0E, 0x00},
    		{0x6C, 0x0F, 0x00},
    		{0x6C, 0x10, 0x1D}, 
    		{0x6C, 0x11, 0x1D},
    		{0x6C, 0x12, 0x01},
    		{0x6C, 0x13, 0x04},
    		{0x6C, 0x14, 0xA1}, 
    		{0x6C, 0x15, 0x00}, 
    		{0x6C, 0x16, 0x00},
    		{0x6C, 0x17, 0x00},
    		{0x6C, 0x18, 0x1B}, 
    		{0x6C, 0x19, 0x00},
    		{0x6C, 0x1A, 0x00},
    		{0x6C, 0x1B, 0x00},
    		{0x6C, 0x1C, 0x00},
    		{0x6C, 0x1D, 0x00},
    		{0x6C, 0x1E, 0x00},
    		{0x6C, 0x1F, 0x00},
    		{0x6C, 0x20, 0x00},
    		{0x6C, 0x21, 0x00},
    		{0x6C, 0x22, 0x00},
    		{0x6C, 0x23, 0x01},
    		{0x6C, 0x24, 0xCF},
    		{0x6C, 0x25, 0x00},
    		{0x6C, 0x26, 0x81},
    		{0x6C, 0x27, 0x00},
    		{0x6C, 0x28, 0x81},
    		{0x6C, 0x29, 0x40},
    		{0x6C, 0x2A, 0xB3},
    		{0x6C, 0x2B, 0x00},
    		{0x6C, 0x2C, 0x95},
    		{0x6C, 0x2D, 0x00},
    		{0x6C, 0x2E, 0x81},
    		{0x6C, 0x2F, 0xC0},
    		{0x6C, 0x30, 0xD1},
    		{0x6C, 0x31, 0xC0},
    		{0x6C, 0x32, 0x81},
    		{0x6C, 0x33, 0x80},
    		{0x6C, 0x34, 0xA9},
    		{0x6C, 0x35, 0xC0},
    		{0x6C, 0x36, 0x02},
    		{0x6C, 0x37, 0x3A},
    		{0x6C, 0x38, 0x80},
    		{0x6C, 0x39, 0x18},
    		{0x6C, 0x3A, 0x71},
    		{0x6C, 0x3B, 0x38},
    		{0x6C, 0x3C, 0x2D},
    		{0x6C, 0x3D, 0x40},
    		{0x6C, 0x3E, 0x58},
    		{0x6C, 0x3F, 0x58},
    		{0x6C, 0x40, 0x45},
    		{0x6C, 0x41, 0x00},
    		{0x6C, 0x42, 0x80},
    		{0x6C, 0x43, 0x38},
    		{0x6C, 0x44, 0x74},
    		{0x6C, 0x45, 0x00},
    		{0x6C, 0x46, 0x00},
    		{0x6C, 0x47, 0x18},
    		{0x6C, 0x48, 0x00},
    		{0x6C, 0x49, 0x00},
    		{0x6C, 0x4A, 0x00},
    		{0x6C, 0x4B, 0xFD},
    		{0x6C, 0x4C, 0x00},
    		{0x6C, 0x4D, 0x0A},
    		{0x6C, 0x4E, 0x96},
    		{0x6C, 0x4F, 0x0A},
    		{0x6C, 0x50, 0x96},
    		{0x6C, 0x51, 0x0F},
    		{0x6C, 0x52, 0x01},
    		{0x6C, 0x53, 0x00},
    		{0x6C, 0x54, 0x00},
    		{0x6C, 0x55, 0x00},
    		{0x6C, 0x56, 0x00},
    		{0x6C, 0x57, 0x00},
    		{0x6C, 0x58, 0x00},
    		{0x6C, 0x59, 0x00},
    		{0x6C, 0x5A, 0x00},
    		{0x6C, 0x5B, 0x00},
    		{0x6C, 0x5C, 0x00},
    		{0x6C, 0x5D, 0x10},
    		{0x6C, 0x5E, 0x00},
    		{0x6C, 0x5F, 0x00},
    		{0x6C, 0x60, 0x00},
    		{0x6C, 0x61, 0x00},
    		{0x6C, 0x62, 0x00},
    		{0x6C, 0x63, 0x00},
    		{0x6C, 0x64, 0x00},
    		{0x6C, 0x65, 0x00},
    		{0x6C, 0x66, 0x00},
    		{0x6C, 0x67, 0x00},
    		{0x6C, 0x68, 0x00},
    		{0x6C, 0x69, 0x00},
    		{0x6C, 0x6A, 0x00},
    		{0x6C, 0x6B, 0x00},
    		{0x6C, 0x6C, 0x00},
    		{0x6C, 0x6D, 0x00},
    		{0x6C, 0x6E, 0x00},
    		{0x6C, 0x6F, 0x10},
    		{0x6C, 0x70, 0x00},
    		{0x6C, 0x71, 0x00},
    		{0x6C, 0x72, 0x00},
    		{0x6C, 0x73, 0x00},
    		{0x6C, 0x74, 0x00},
    		{0x6C, 0x75, 0x00},
    		{0x6C, 0x76, 0x00},
    		{0x6C, 0x77, 0x00},
    		{0x6C, 0x78, 0x00},
    		{0x6C, 0x79, 0x00},
    		{0x6C, 0x7A, 0x00},
    		{0x6C, 0x7B, 0x00},
    		{0x6C, 0x7C, 0x00},
    		{0x6C, 0x7D, 0x00},
    		{0x6C, 0x7E, 0x00},
    		{0x6C, 0x7F, 0x04},
            {0x64, 0x74, 0x01} //ENABLE INTERNAL EDID



  • Hi,

    As per your configuration "98 00 02" your input format seems 800×600@72Hz,Pixel clock is 50Mhz. When dual LVDS transmitter enabled, the LVDS output clock to drive the identical panels will be running at half the input clock rate (25MHz). So its under TX PLL lock with GEAR setting 000 (i.e 25 MHz to 40 MHz). This is the reason for not locking with 010.

    Pixel Clock = Horizontal total pixels x Vertical total pixels x Vertical frequency.

    Note: Single mode LVDs, the input pixel rate is equal to the HDMI pixel.
              Dual mode LVDS, the pixel rate is half of the single or the HDMI pixel. 



  • Hi,

    I don't use "free run" mode, so UG907 recommnends:

    If free run and decimation are not required, it is recommended to set the following configuration for HDMI mode:
    • PRIM_MODE[3:0] = 0x06
    • VID_STD[5:0] = 0x02

    that mean 98 01 06  and 98 00 02.

    I don't have input resolution 800x600@72Hz! 

    I use HDMI RX with various resolutions and with most of them works, but I have problem with input resolution:
    1280x800@60Hz  with HDMI frequency od 82.9MHz (TX LVDS frequency in dual mode is 41.45 MHz).

    if I set TX PLL gear to 000 works (with 010 does not) even manual say that if I have freq > 40MHz I must use PLL gear of 010!



  • Hi,

     For 1280x800@60Hz ,the pixel frequency is 71Mhz.

     Horizontal total pixels= 1440 Pixels

     Vertical total pixels= 823

     Pixelclock= 1440*823*60= 71.107200Mhz

    Please refer Vesa document for more information about the input timing.



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