We've a custom box with several ADV7511 chips outputting video from an FPGA.
We initialize the ADV to run at a constant resolution DVI output 1024x768p60, and this works okay.
To detect the hot-plug status, we poll register 0x42 every few seconds. The interrupt for HPD is also active, but isn't reliable on our board (hence the polling) because of too may daisy-chained gpio expanders.
What we experience is that sometimes after say a full week of running, we suddenly get I2C read errors on reading register 0x42. Once this happens, it persists and all subsequent reads of 0x42 fail.
Is there some state the chip can be in that this register is no longer accessible? As far as I can see in the datasheet, this is one of the registers that remains accessible regardless of what parts of the chip we powered down.
I've added a bunch of debugging to be sure, but I got the impression that reading the interrupt status register at 0x96 did work okay, and other I2C devices are also still responding on the same bus. It'll take weeks before this error triggers again in the remote location where the hardware is running, but it has been observed multiple times.
I know of no effect that would show as you've described. Register 0x42 should always be readable in any power state as long as the chip has good power. I assume you are getting a NACK back on the reads and power cycling the chip fixes the problem.
The only other thing I can think of is there was a power glitch and the PD/AD pin changed the address the ADV7511 responses to (0x72->0x7A). When if fails does it respond to the other address?
I was afraid the answer would be something like that... And the PD/AD pin is hard wired, so it isn't likely to change address. But I'll try and probe the 7A address (or 3D depending on where you put the 7 bits) if we ever see the bug.
We'll probably have to look into the I2C controller (FPGA) or the I2C bus multiplexer as a source of problems.