ADV7612 Image Mosaic clock difference problem

Dears,

      There's aplication about ADV7612, the details signal block as below:

3280*1080@60HZ soure--->Dual LInk--->ADV7612*2---->FPGA---->ADV7511--->Display

The Fpga mainly process  image mosaic (from two ADV7612), In this application, the FPGA get the output data from two ADV7612 have up to 8 clock cycles after device re-power and sometimes differ one clock cycle. So is there any constant clock cycle or some other advice for this application?

Parents
  • 0
    •  Analog Employees 
    on Aug 20, 2019 1:55 PM

    1) 3280x1080p60 would have a clock rate of ~225MHz.  The ADV7511 input clock limitation is 165MHz.  So the above flow will not work unless the FPGA is down scalling the image.  When the ADV7511 states it's a 225MHz transmitter it is referring to the transmitter transmitting 1080p60 12-bit color (deep color) which would have a 222.75MHz TMDS clock versus a 1080p60 8-bit color TMDS clock rate of 148.5MHz.

    2) The ADV7612 is not able to run in dual link mode.  There is no way to synchronize the outputs between the 2 chips.  At best the FPGA would have to do the synchronization.

    3) ADI does not have a single chip dual link DVI receiver.

Reply
  • 0
    •  Analog Employees 
    on Aug 20, 2019 1:55 PM

    1) 3280x1080p60 would have a clock rate of ~225MHz.  The ADV7511 input clock limitation is 165MHz.  So the above flow will not work unless the FPGA is down scalling the image.  When the ADV7511 states it's a 225MHz transmitter it is referring to the transmitter transmitting 1080p60 12-bit color (deep color) which would have a 222.75MHz TMDS clock versus a 1080p60 8-bit color TMDS clock rate of 148.5MHz.

    2) The ADV7612 is not able to run in dual link mode.  There is no way to synchronize the outputs between the 2 chips.  At best the FPGA would have to do the synchronization.

    3) ADI does not have a single chip dual link DVI receiver.

Children