ADV7612 Image Mosaic clock difference problem


      There's aplication about ADV7612, the details signal block as below:

3280*1080@60HZ soure--->Dual LInk--->ADV7612*2---->FPGA---->ADV7511--->Display

The Fpga mainly process  image mosaic (from two ADV7612), In this application, the FPGA get the output data from two ADV7612 have up to 8 clock cycles after device re-power and sometimes differ one clock cycle. So is there any constant clock cycle or some other advice for this application?