Using ADV7393 as black burst generator output on RGB or YPbPr

Hi,

I have a requirement for black Burst Sync Signal generation on RGB/YPbPr output of ADV7393 Chip.

I intend to Ground the Pixel data bus and drive only the HSYNC and VSYNC signals with the 27Mhz clock.

Is there any technical difficulties here and what should be the best mode of operation of the device to set this up.

I have gone through this Q&A https://ez.analog.com/video/f/q-a/6461/adv7393-as-black-burst-generator-but-problem-locking-to-external-h-v/20769#20769

I am not sure whether this issue is resolved.

Can someone give a clarification on this.?

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  • 0
    •  Analog Employees 
    on Aug 20, 2019 6:36 AM over 1 year ago

    Hi,

     Please make sure the following i2c writes are taken care from your side for SD blackbar test pattern.

       0x00 = FCh ; Power up DACs and PLL
       0x02 = 24h ; Enable Black bar test pattern // 04 RGB component output
       0x82 = 49h ; Pixel data valid and setup DACs
       0x84 = 40h ; Enable test pattern
    For more details about ED/HD blackbar test pattern configuration, Please refer Internal test pattern generation section.

    Thanks,

    Poornima

  • Hi, 

    my understanding from the previous threads was that the internal Test pattern Generator does not use the SYNC information given on the HSYNC and VSYNC Pins. It just uses the 27MHz clock to generate the pattern selected.

    My intention here is not to use the internal test pattern Generator and drive the SYNC signals with the pixel data bus grounded, thus generating a black burst signal on the configured output interface.

  • 0
    •  Analog Employees 
    on Aug 20, 2019 10:01 AM over 1 year ago in reply to whitefalcon

    Hi,

    my understanding from the previous threads was that the internal Test pattern Generator does not use the SYNC information given on the HSYNC and VSYNC Pins. It just uses the 27MHz clock to generate the pattern selected.

      Yes. The test pattern only uses the clock input, it does not use the external sync signals.

    My intention here is not to use the internal test pattern Generator and drive the SYNC signals with the pixel data bus grounded, thus generating a black burst signal on the configured output interface.

     We don't have any specific requirements or recommendations for Genlock. Please refer here https://ez.analog.com/video/f/q-a/11249/using-adv7391-for-genlock---black-burst

     Note:  Generally Black burst is a composite video signal with a totally black picture. It is used to
    synchronize video equipment so the video outputs are aligned.

    Thanks,

    Poornima

  • Hi,

    Does this mean the ADV7393 device can function as a Genlock source without any additional modifications? 

    If not, could you please suggest an alternative device which can generate Genlock signal from the H,V,F signals driven to it?

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