I use the ADV7393 in square pixel mode with EAV/SAV input and a 24.54MHz clock to generate an NTSC CVBS signal.
This mode is all detailed in the data sheet and works just fine. I have no issues with this configuration and I think it verifies my hardware is functional, my I2C programming works and my digital data stream is correct.
Now the twist.
My implementation needs to lock this signal to a legacy 30Hz system. I thought I could pull the pixel clock rate down to the 24.57MHz range and leave everything else the same to achieve this. I was wrong. At some point between 24.54 and 24.57 every monitor I have tried quits decoding color and we end up looking at a greyscale image.
The CVBS signal from the ADV7393 looks fine on the oscilloscope. With careful measurement we can see the color burst and all the other timing scale by 0.1%. The best I can tell, the ADV7393 is working fine at this rate. It may be that monitors can detect this small frequency shift. All I know for certain is the system does not work right now. It would be great if an ADV7393 register adjustment might help.
I expect my problem is obvious to one of the video experts in this community. I could sure use some advice, whether it relates to the ADV7393, CVBS, monitors, or clocking.
As per specification, For NTSC square pixel mode.It work till 29.97Hz frame rate with 24.54Mhz input clock. Anyhow let me check with part specialist on this.