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ADV7182A Init and strange images

Hi,

My custom board has ADV7182 to get images from two cameras and decode to my microcontroller. I've configured by I2C the init in "Free Run Mode" and in "Colors Bar Mode". In free run mode I could see that the images showed in LCD has relation to camera movements, but fully abstract. In colors bar mode I could see some pixels coloured, but without synchronization.

This I could get.

I followed the instructions from "5340.ADV7182RSD_revC" and "ADV7182CUST-VER.5.0.txt".

Any suggestion?

Thanks.

  • Hi,

    It seems like problem with micro-controller timing. But We don face any issue with freerun using ADV7182. Please crosscheck your schematic at design support file.

    Always you are not getting proper colorbar output in freerun ? This is not happening with bluescreen freerun output?

    If there is anyway to do this in ADV7182 would be great?

         ADV7182 does not support CSC.

    Thanks,

    Poornima

  • Hi,

    Yes always. In Blue mode I have a green screen...

    Can you explain after the VSYNC signal how many pixels are sent to complete a line?

    Thnaks.

  • Hi,

     To know more about video related details,Refer below attached video-demy.Pdf

     PDF

    Thanks,

    Poornima

  • Hi,

    Thanks for the book, it was very helpfull!

    I could implement the conversion and it is working well. But Something strange I have in received data. I'm using HSYNC and VSYNC signals from ADV7182, but in data received I get the sync codes too (SAV and EAV...), and I needed to implement a code to remove this, but I spent process with this...

    Is there a way to remove the sync codes in data (FF 00 00 YY)? And use only the HSYNC and VSYNC signals.

    Thanks,

    Anderson

  • Hi,

     Have you tried by clearing the NEWAVMODE in register 0x31?

    Thanks,

    Poornima

  • Hi ,

    Thanks for reply.

    Yes, I've tried this command, but it doesn't make effect.

    ADV7182_Write(0x31, 0x02);									/* Enable NEWAVMODE */

    Is there a way to ADV7182 doesn't send the embedded sync codes? Working only with HSYNC and VSYNC signals?

    Here is my command set:

    ADV7182_Write(0x0F, 0x80);			/* Resets device */
    	  Delay_ms(20);
    	  ADV7182_Write(0x0F, 0x00);			/* Exit Power Down Mode */
    	  ADV7182_Write(0x13, 0x00);			/* Select 28.63636 MHz Clock Input */
    	  ADV7182_Write(0x52, 0xCD);			/* Set optimized IBIAS for AFE in Single Ended CVBS Format */
    	  ADV7182_Write(0x00, 0x00);			/* Select AIN1 as INPUT */
    	  /* ADI Steps */
    	  ADV7182_Write(0x0E, 0x80);				/* ADI Required Write; Reset Current Clamp Circuitry (step 1) */
    	  ADV7182_Write(0x9C, 0x00);				/* ADI Required Write; Reset Current Clamp Circuitry (step 2) */
    	  ADV7182_Write(0x9C, 0xFF);				/* ADI Required Write; Reset Current Clamp Circuitry (step 3) */
    	  ADV7182_Write(0x0E, 0x00);				/* ADI Required Write; Reset Current Clamp Circuitry (step 4) */
    
    	  /* Fast Switch Mode was skipped */
    
    	  ADV7182_Write(0x17, 0x41);			/* Select SH1 Chroma Shaping Filter */
    	  ADV7182_Write(0x03, 0x0C);			/* Enable Pixel & Sync output drivers */
    	  ADV7182_Write(0x04, 0x07);			/* Power-up INTRQ, HS and VS/FIELD/SFL pad */
    	  ADV7182_Write(0x1D, 0x40);			/* Enable LLC Output Driver */
    
    
    	  ADV7182_Write(0x31, 0x02);									/* Enable NEWAVMODE */

    Thanks,

    Anderson

  • Hi

    Do you have any information about the sync codes in ADV7182A? If there is a way to work only with external signal (HSYNC and VSYNC).

    Thanks.

    Anderson

  • Hi,

    The ADV7182 extracts syncs embedded in the analog input video signal. Currently there is no support for external HS/VS inputs.

     ADV7182A output VSYNC and FIELD output signals, as well as the generation of embedded AV codes. Note that the VSYNC and FIELD signalscan be output on the VS/FIELD/SFL pin or the HS pin
     When TIM_OE is 1, HS and VS/FIELD/SFL are forced active all the time.But by default all are tristated.

     FLD_OUT_SEL[2:0](Address 0x6B) bits select whether the VS/FIELD/SFL pin outputs vertical sync, horizontal sync, field sync, data enable (DE), or subcarrier frequency lock (SFL) signals. Note that the VS/FIELD/SFL pin must be active for this selection to occur.The HS pin (Address 0x6A) is set to output horizontal sync signals as the default. Note that the HS pin must be active for this selection to occur.

     For more details refer Page17 in ADV7182A datasheet and configure 0x04 instead of tristating the
    TIM_OE(timing signal output enable).

    Thanks,

    Poornima

  • Hi,

    Thanks for replay.

    Thanks for the information, I could verify all setup and changing some parameters, but it doesn't fix my issue.

    I would like to know if ADV7182 can output ONLY image data, without embedded sync codes in data! Please take a look in TVP5150 datasheet page 30, you can select if output data is with or without embedded sync codes:

    000 = 8-bit 4:2:2 YUV with discrete sync output

    111 = 8-bit ITU−R BT.656 interface with embedded sync output (default)

    With discrete output I can work only with HSYNC and VSYNC signals.

    Sorry to compare to other chip but I need to fix this issue, my project is in final stage..

    Regards,

    Anderson

  • Hi,

     But this is not possible in ADV7182A. ADV7182 converts analog video formats into a digital 8-bit ITU-R BT.656 video stream. We use the term ITU-656 in our receivers to describe output of digital video with embedded syncs (SAV/EAV codes).

     But i beleive by using FLD_OUT_SEL[2:0] register you can output DE(Data enable) information. DE indicates active video. During this interval the TMDS lines will have video on them.  But when DE is low and in HDMI mode TMDS will carry only info and audio packets.

    Thanks,

    Poornima