ADV7184-ADV7391 genlock problems

   Hello!
   We create the device for superposition overlay graphics on the television image presented by composite video signal cvbs_in. On an device

output it is necessary to form composite video signal cvbs_out which should be locked to cvbs_in. Color subcarrier frequency and phase should be

same, as at cvbs_in.
   The structure of our device is shown in the attachment.
   Digital video mixer combines video_in_data and overlay_video_data. Genlock control compensates a processing delay of video decoder and video

encoder, therefore video timing of cvbs_in and cvbs_out is absolutely identical. Video_out_data are clocked impulses LLC_27MHz from video

decoder, the SFL signal is connected directly from decoder to encoder.
   Digital format of video_in_data and video_out_data is 8-bit ITU-R BT.656 YCbCr 4:2:2.
   The device contains the quartz crystal oscillator making system clock xtal_27MHz. Input clock for video decoder xtal_28.636MHz produces a

frequency synthesizer in conformity with: 28.636MHz = 27MHz *35/33.
   In our device we have two problems.

  1. Subcarrier frequency lock.
   1.1. Encoder SFL input is disabled.
   ADV7391 register 0x84 bits (2:1) = 00.
   Cvbs_in and cvbs_out color subcarrier frequencies are strictly equal, their mutual phase is stable, but not equal zero. It is obvious, that cvbs_in

video source and ours ADV7391 encoder calculate frequency of color subcarrier identically.
   1.2. Decoder SFL output and encoder SFL input are enabled.
   ADV7184 register 0x04 bits (1) = 1.
   ADV7391 register 0x84 bits (2:1) = 11.
   Cvbs_in and cvbs_out color subcarrier frequencies are not equal (differ a few Hz), their mutual phase is instable. It happens in both PAL and

NTSC modes. It is revealed, that frequency of color subcarrier of cvbs_out depends on frequency xtal_28.636MHz, but does not depend from

cvbs_in.
   It is our first problem.
   1.3. Decoder SFL output is disabled, encoder SFL input is enabled.
   ADV7184 register 0x04 bits (1) = 0.
   ADV7391 register 0x84 bits (2:1) = 11.
   Cvbs_out completely degrades - color subcarrier is absent, video sync is disturbed. It, maybe, is normal.
   1.4. Video decoder has such parameter:
        Fsc Subcarrier Lock Range - + /-1.3 Hz (Typ)
        (Lock Time Specifications, ADV7184 Data Sheet, page 6)
        What does it amount to?

   Thus, we cannot achieve our purpose - to find equability of frequency and a phase of color subcarrier of cvbs_in and cvbs_out. What can you

advise us?

  2. Video decoder PLL jitter.
   In NTSC mode, if frequency LLC_27MHz on an output of the video decoder becomes close to frequency of the crystal oscillator xtal_27MHz (a

difference of frequencies less than 200 Hz), arises jitter of signals LLC_27MHz and video_in_data. This jitter (up to 100 ns), finally, causes

handicapes in work of the video encoder on an output cvbs_out. If the difference of frequencies LLC_27MHz and xtal_27MHz is more than 200 Hz,

all is OK.
   In PAL mode, all always OK.
   It is our second problem.

   We hope for your help in the resolve of above problems.

   Best Regards,
   Alexander.

GENLOCK-bd.pdf
  • 0
    •  Analog Employees 
    on Mar 3, 2012 1:16 AM over 9 years ago

    Hello,

    This looks like a duplicate of this issue: http://ez.analog.com/message/44211#44211.  I've posted a response there... best to just use one thread .

    Dave

  •    Hi, Dave.

       We have rather other problem, than discussed in  http://ez.analog.com/message/29809#29809 .

       1. TV monitor connected to our video output cvbs_out shows a good picture, but when SFL is enabled, then the oscilloscope shows, that color subcarrier burst frequercies of cvbs_in and cvbs_out are not equal one another.

    In mentioned above discussion you wrote:

    " You CAN use the SFL signal directly if your processing has the same line timings as the original."

    Our processing unit is clocked LLC_27MHz also has line timing absolutely same as video decoder ADV7184.

       2. Why video decoder PLL jitter appears at NTSC mode only? XTAL input pin of ADV7184 is connected to the clock source 28.636MHz..

       Alexander

  • 0
    •  Analog Employees 
    on Mar 6, 2012 2:25 AM over 9 years ago

    Hi Alexander,

    My reply there was to point to that thread...  It's not the clock-- it's the variance in the line timings that have to be compensated for, otherwise there would be no need for SFL since the variance would be in the LLC. Unfortunately, he never did say what he did to make it work-- you might try to send him a private message.

    Are you actually using a 28.636Mhz crystal?  That is what is required.

    Dave

  • Hi Dave.


    About subcarrier frequency lock I have executed some researches and have found out:
    Video decoder calculates SFL data in the form of 22 bits "genlock telegram" Fsc PLL increment(21:0) in conformity with

      SFL_data = 35/33 * (Fsc_in / Fxtal) * 2E24,        (1)

       where Fsc_in - color subcarrier frequency of video input CVBS_in,
                  Fxtal - crystal frequency 28.636MHz = 35/33 * 27MHz.

    In SFL mode, video encoder calculates subcarrier frequency of video output CVBS_out in conformity with

       Fsc_out = SFL_data * Fllc / 2E24,                     (2)

      where Fsc_out - color subcarrier frequency of video output CVBS_out,
                 Fllc - frequency of line-locked clock LLC_27MHz of video decoder, connected to encoder CLK input.
    From (1) and (2) follows:

       Fsc_out = 35/33 * (Fllc / Fxtal) * Fsc_in.

    Hence, Fsc_out is strictly equal Fsc_in ONLY if Fxtal is strictly equal 35/33 * Fllc. This condition practically is never executed, because crystal oscillator of CVBS_in source and crystal connected to video decoder both have an error of nominal frequency. For example, at crystals frequency tolerance plus-minus 50ppm we have error Fsc_out relatively Fsc_in up to 100ppm, or approximately 400Hz, i.e. SFL system works not correctly.
    The reason of this mistake that for measurement Fsc_in video decoder uses Fxtal, but for digital synthesis Fsc_out video encoder uses Fllc.
    Thus, if my reasonings are true, the conclusion follows, that chipset ADV7184-ADV7391 with ADI SFL system do not provide the requirement of our application.
    What can you tell to me in this occasion?

    Alexander.

  • 0
    •  Analog Employees 
    on Mar 20, 2012 6:43 PM over 9 years ago

    Hi Alexander,

    The SFL that the ADI decoders use is proprietary and basically tells the encoder the line length variations to account for LLC that isn't stable from the source.

    It's meant only for connecting an ADI decoder directly to an ADI encoder with nothing in between.  For that reason, I think what you are trying to do with it wouldn't work-- you'd need to resync in the device in the middle.

    However, the thread that was linked indicated that the customer was able to make it work.  He just never came back and said what he did.

    Dave