ADV7391/ADV7393 I2C Problem

Hello everyone,

This is not a question but rather a design note for people who are planning to use ADV739x chips. Especially for people having problems on I2C communication with ADV739x chips.

I have spent a fair amount of time to solve this problem. I am glad I did. But I would prefer to find a post about this. That's why I am writing the solution here.

I2C Problem

Problem Statement: Although everything (timing, i2c addresses, waveforms etc.) seems correct, ADV739x does not send the ACK bit.

Solution: If your design complies with all the timings related to I2C part but you still do not get any ACK bit. 

Please make sure that you leave a hold time (1us min.) before changing the SDA line after every falling edge of SCL.

As far as I checked the datasheet, this is not mentioned. The waveform should look like this:  

Normally, in an I2C communication, SDA line is sampled on the rising edges of SCL. I think this is little different for ADV739x. There should be some delay on SDA line so that after falling edge instants of SCL, the SDA should change with a 1us min. delay.



small corrections
[edited by: sgenc at 7:31 AM (GMT 0) on 8 Aug 2019]
  • 0
    •  Analog Employees 
    on Aug 7, 2019 2:36 PM over 1 year ago

    Thank you for pointing out the SDA hold requirement not being listed in the data sheet.

    Normally I2C masters change SDA at the mid-point of a SCL low period so this data hold requirement gets meet by default.  You might run into problems if you bit-bang SDA/SCL lines and don't provide the hold time.

    I've attached a couple of documents with more I2C specifications.  Especially check out Figure 31 in the I2C_BUS_SPEC.... doc.

    PDF PDF