We use four ADV7619KSVZ-P chips to receive 4k HDMI video signals (3840 x 2160 @ p30). We are using FPGA to receive the digital data from the four ADV7619 chips. On our test, we found one of four video images received by the four ADV7619 chips twisting. When we check the video clock output at LLC pin (Pin 62) of ADV7619KSVZ-P, we found the quality of the clock signals from these four ADV7619KSVZ-P chips are not good. From our test we found that to increase power supply voltage for PVDD and CVDD from 1.80V to 1.88V, the quality of the clock signals from LLC pins were improved. The video twisting issue disappeared. However, when testing the board in a 50C chamber, the video twisting issue appeared at another HDMI channel. Here are my questions:
1. What factors might affect the signal qualify for the clock output from LLC pin?
2. Any idea why the video twisting is happening?
3. Do you have any suggestions to debug this issue?
4. ADV7619KSVZ-P data sheet indicate that ADV7619KSVZ-P support DDR mode for the video data output. However, datasheet also states that "DDR can be supported with LLC clock frequency up to 50 MHz (video modes with original pixel clock lower than 100 MHz, such as 1080i60)." Do you think we could use DDR mode to receive 3840 x 2160 @ p30 video?