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Video image twisting with ADV7619 to receive 4K HDMI video stream

Hello Support,

We use four ADV7619KSVZ-P chips to receive 4k HDMI video signals (3840 x 2160 @ p30). We are using FPGA to receive the digital data from the four ADV7619 chips. On our test, we found one of four video images received by the four ADV7619 chips twisting. When we check the video clock output at LLC pin (Pin 62) of ADV7619KSVZ-P, we found the quality of the clock signals from these four ADV7619KSVZ-P chips are not good. From our test we found that to increase power supply voltage for PVDD and CVDD from 1.80V to 1.88V, the quality of the clock signals from LLC pins were improved. The video twisting issue disappeared.  However, when testing the board in a 50C chamber, the video twisting issue appeared at another HDMI channel. Here are my questions:

1. What factors might affect the signal qualify for the clock output from LLC pin?

2. Any idea why the video twisting is happening?

3. Do you have any suggestions to debug this issue?

4. ADV7619KSVZ-P data sheet indicate that ADV7619KSVZ-P support DDR mode for the video data output. However, datasheet also states that "DDR can be supported with LLC clock frequency up to 50 MHz (video modes with original pixel clock lower than 100 MHz, such as 1080i60)." Do you think we could use DDR mode to receive 3840 x 2160 @ p30 video?

Thanks,

De

Top Replies

  • FormerMember
    FormerMember
Aug 9, 2019 in reply to Dli5678 +1 verified

you are losing horizontal lock.  Check the stability of the TMDS input clocks and the HS output clocks

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  • FormerMember
    0 FormerMember
on Aug 1, 2019 5:18 PM

Hi De

First of all when you say twisting I assume is horizontally tearing, I.e. torn lines are really shifted left or right in relationship to where they should be.

Items to check: (not in any specific order)

1) PVDD must be very clean.  Noisy PVDD will affect TMDS_PLL_LOCK which can effect the output video.  Monitor TMDS_PLL_?_RAW and TMDS_PLL_LOCK bits to see if they are changing.

2) Check the temperature of the chip when in the oven at 50C.  The chip might be over heating if layout has improper PCB cooling area or other general cooling problems. 

3) Clock and data output can be effected by layout.  I'd check the design with some signal integrity tools to make sure you're not getting any strange reflections or loading issues.  Maybe check different DR_STR and DR_STR_CLK setting to get a better waveform.

4) Check out the user guide section on LLC Controls.  This allows you to phase shift the LLC clock in relation to the data signals.  This phase relationship needs to be checked at least once for each board layout.  I'd do a Schmoo plot of all 32 phases and pick the best one to initialize the chip with on power up.

5) Regarding DDR mode, DDR clock is limited to 50MHz.  3840x2160P30 has a clock of ~300MHz which for double wide bus would be 150MHz, going DDR on a double wide bus the clock would be 75MHz exceeding DDR limit of 50MHz

Reply
  • FormerMember
    0 FormerMember
on Aug 1, 2019 5:18 PM

Hi De

First of all when you say twisting I assume is horizontally tearing, I.e. torn lines are really shifted left or right in relationship to where they should be.

Items to check: (not in any specific order)

1) PVDD must be very clean.  Noisy PVDD will affect TMDS_PLL_LOCK which can effect the output video.  Monitor TMDS_PLL_?_RAW and TMDS_PLL_LOCK bits to see if they are changing.

2) Check the temperature of the chip when in the oven at 50C.  The chip might be over heating if layout has improper PCB cooling area or other general cooling problems. 

3) Clock and data output can be effected by layout.  I'd check the design with some signal integrity tools to make sure you're not getting any strange reflections or loading issues.  Maybe check different DR_STR and DR_STR_CLK setting to get a better waveform.

4) Check out the user guide section on LLC Controls.  This allows you to phase shift the LLC clock in relation to the data signals.  This phase relationship needs to be checked at least once for each board layout.  I'd do a Schmoo plot of all 32 phases and pick the best one to initialize the chip with on power up.

5) Regarding DDR mode, DDR clock is limited to 50MHz.  3840x2160P30 has a clock of ~300MHz which for double wide bus would be 150MHz, going DDR on a double wide bus the clock would be 75MHz exceeding DDR limit of 50MHz

Children on Aug 9, 2019 9:18 AM in reply to Dli5678

you are losing horizontal lock.  Check the stability of the TMDS input clocks and the HS output clocks