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AD9889B Not Recommended for New Designs
The AD9889B is a 165 MHz, high definition multimedia inter-face (HDMI®) v. 1.3 transmitter. It supports HDTV formats up to 1080p, and computer graphic...
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AD9889B on Analog.com

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AD9889B and 1080p60 problem



		

			

									
					    Jacky-zheng
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jul 1, 2012 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hello,
    
 
    I am using an AD9889B,sucessfully transmitting 720p60 and 480p60 signals.
    
 
    Now I tried to transmit 1080p60.
    
 
    AD9889B corrently recognizes the mode that I send to it by reading these registers(R0x3D=0x10,R0x41=0xF8,R0x42=0x10,all circuits powered up and Hot plug active),but the display is black.I've tried many diffrent displays(samsung and others),all displays are black.
    
 
    I modify R0xA2 and R0xA3 to 0X87,and change the timing sequence following EIA-CEA-861-D(verified with a scope),and using videoclock of 148.5MHz,but it's not working.
    
 
    I've tried 1280*768 60Hz too,the videoclock of 108MHz,the display is sign good and black from time to time.
    
 
    I am not using HDCP.
    
 
    Any other regiter must be modfied?
    
 
    many thanks
    
 
    Tom
    
								
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	
    
		
	
    















    
	
    
	
    
					



			








	
	
	
	



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													0
							
			
				
									
							        
			
			
			
        
            
			                            
                        
                on Jul 5, 2012 11:15 PM
            
            
					
        
	
        

		
		
        
					
        Hi Dave,
        
 
        My system can't work at 1080P60 yet, as before still the R0x9E[4]=0 when VCLK running at 148.5MHz.
        
 
        The bandwidth of our scope is only 200M, so it can't  correctly test the VCLK which running at 148.5MHz. I've contacted with the company who produce the scope, the FAE told me this scope only can correctly test signals which running 40MHz! 
        
 
        I've contacted with the FAE of altera's,who told me the pin of cyclone4 can output clock=200MHz friendly, I use a multimeter to test the FPGA's output pin, which is LVCMOS3.3.
        
 
        V=1.61 when VCLK=74.25MHz
        
 
        V=1.75 when VCLK=108MHz
        
 
        V=1.90 when VCLK=148.5MHz
        
 
        The FAE lay to me?!
        
 
        There is lots of niose on PVDD(400mv) which was be told by the scope, but I can't trust the scope anymore!
        
 
        My question is:
        
 
        If there is so much noise on PVDD, I think AD9889B can't lock VCLK which running at 74.25MHz, But AD9889B can lock VCLK! why this happended?
        
 
        If the noise isn't strong enough, AD9889B can lock the VCLK which running at a lower frequency?
        
 
        AD9889B can lock the VCLK=108MHZ by modify R0x98=0x07 to 0x0B, and why?
        
 
        Many thanks!
        
 
        Tom
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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													0
							
			
				
									
							        
			
			
			
          
            
			                            
                        
                on Jul 5, 2012 11:15 PM
            
            
					
          
	
          

		
		
          
					
          Hi Dave,
          
 
          My system can't work at 1080P60 yet, as before still the R0x9E[4]=0 when VCLK running at 148.5MHz.
          
 
          The bandwidth of our scope is only 200M, so it can't  correctly test the VCLK which running at 148.5MHz. I've contacted with the company who produce the scope, the FAE told me this scope only can correctly test signals which running 40MHz! 
          
 
          I've contacted with the FAE of altera's,who told me the pin of cyclone4 can output clock=200MHz friendly, I use a multimeter to test the FPGA's output pin, which is LVCMOS3.3.
          
 
          V=1.61 when VCLK=74.25MHz
          
 
          V=1.75 when VCLK=108MHz
          
 
          V=1.90 when VCLK=148.5MHz
          
 
          The FAE lay to me?!
          
 
          There is lots of niose on PVDD(400mv) which was be told by the scope, but I can't trust the scope anymore!
          
 
          My question is:
          
 
          If there is so much noise on PVDD, I think AD9889B can't lock VCLK which running at 74.25MHz, But AD9889B can lock VCLK! why this happended?
          
 
          If the noise isn't strong enough, AD9889B can lock the VCLK which running at a lower frequency?
          
 
          AD9889B can lock the VCLK=108MHZ by modify R0x98=0x07 to 0x0B, and why?
          
 
          Many thanks!
          
 
          Tom
          
			
          

		
		
		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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