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AD9889B and 1080p60 problem


I am using an AD9889B,sucessfully transmitting 720p60 and 480p60 signals.

Now I tried to transmit 1080p60.

AD9889B corrently recognizes the mode that I send to it by reading these registers(R0x3D=0x10,R0x41=0xF8,R0x42=0x10,all circuits powered up and Hot plug active),but the display is black.I've tried many diffrent displays(samsung and others),all displays are black.

I modify R0xA2 and R0xA3 to 0X87,and change the timing sequence following EIA-CEA-861-D(verified with a scope),and using videoclock of 148.5MHz,but it's not working.

I've tried 1280*768 60Hz too,the videoclock of 108MHz,the display is sign good and black from time to time.

I am not using HDCP.

Any other regiter must be modfied?

many thanks


  • Hi Tom,

    What version of the AD9889B are you using? How is it marked on the chip?


  • Dear Dave,

    It's AD9889BBSTZ-165,-165 means the videoclock can running up to 165MHz?

    We use a FPGA(altera cyclone4) to connect with AD9889B,and found that the videoclcok running good when lower than 80MHz but not good faster than 80MHz,It looks like it was superimposed DC level on videoclcok(500mv),and we checked PVDD also,and found it's not clean enough(400mv noise).The PLL of AD9889B lost lock when the vedioclock running above 80MHz.

    Is there any good idea with my case?

    By the way,Could you tell me some details about the PLL of AD9889B?

  • Hi Tom,

    Yes -165 can run up to 165Mhz inputs.

    It sounds like you have issues with your PCB if you are seeing the clock degrade at the higher frequencies and lots of noise on PVDD.  You won't get the AD9889B to work with any settings in that condition.  I'd suggest adding bulk capacitance to try to quiet the power supply for PVDD-- is it isolated from the other power supplies.

    If you can increase the current drive on the VCLK from the FPGA, that might help as well. You might also need termination on that line.


  • Hi Dave,

    My system can't work at 1080P60 yet, as before still the R0x9E[4]=0 when VCLK running at 148.5MHz.

    The bandwidth of our scope is only 200M, so it can't  correctly test the VCLK which running at 148.5MHz. I've contacted with the company who produce the scope, the FAE told me this scope only can correctly test signals which running 40MHz!

    I've contacted with the FAE of altera's,who told me the pin of cyclone4 can output clock=200MHz friendly, I use a multimeter to test the FPGA's output pin, which is LVCMOS3.3.

    V=1.61 when VCLK=74.25MHz

    V=1.75 when VCLK=108MHz

    V=1.90 when VCLK=148.5MHz

    The FAE lay to me?!

    There is lots of niose on PVDD(400mv) which was be told by the scope, but I can't trust the scope anymore!

    My question is:

    If there is so much noise on PVDD, I think AD9889B can't lock VCLK which running at 74.25MHz, But AD9889B can lock VCLK! why this happended?

    If the noise isn't strong enough, AD9889B can lock the VCLK which running at a lower frequency?

    AD9889B can lock the VCLK=108MHZ by modify R0x98=0x07 to 0x0B, and why?

    Many thanks!


  • Hi Tom,

    As you have found, I don't think there is anyway the part can work properly in your environment with VCLK so far out of specification, period.

    Register 0x98 has to do with settings found to work during characterization. Any setting other than 0x7 has not been found to work reliably across temperature / voltage / frequency.

    As you lower the clock rate, you get more margin for error and it will work more often despite issues. It's not the basis for a reliable system though.


  • Hi Dave,

    I think I tested noise on PVDD with a wrong way, I'll test it on tommorow.

    My question is:

    How could I set up my scope? the bandwidth of the scope is 200M,Someone teaches me that must do these settings:

    1: testing bandwidth<=20M

    2: deal with the probe carefully, length of the ground wire<=1cm

    Are these right?

    Maybe noise is too strong, I'll check it, thanks from my heart.


  • Hi Dave,

    I've tested the noise of power supply,The scope told me Vp-p=140mv,I checked document of AD9889B and found noise of power supply=50mv Vp-p, then I go to internet,someone told me the meaning of noise on power supply is about 1/6 of Vp-p, I'm confused???? Counld my power meet the requirement of AD9889B?

    By the way,Would you please give me the complete details about register setting of AD9889B?

    I give AD9889B like these:

    RGB:              4:4:4;  8bit

    H,V and DE:    separate H,V and DE

    data bus:         D[23:0]

    polarity:           High(I'm not sure about this...there's no words to sign polarity of syncs and DE when these signals running separately.

                                  what's kind of polarity syncs and DE signals AD9889B needed,High or low?)

    HDCP:             No HDCP

    Audio:              No audio

    Output: 1080P@60

    Output:  720P@60

    So much appreciation!


  • Hi Tom,

    You will find scripts for many modes on the Design Support Files page of ADV7441A-- ver 2.0 scripts use the AD9889B as the HDMI TX.  The bottom part of each script are the settings for AD9889B for each particular configuration.

    If your VCLK is out of specification, it won't matter if your power supply is noisy or not.  It still won't work. The maxumum allowed power supply noise is 50mv peak to peak-- it's in the data sheet.


  • Dear Dave,

    I found some differences about layout between ours and that is recommended by you. I see that there is a isolated square ground on the top layer in document <AD9889B_ATVEB_layout> but isn't for ours! Is this a necessary thing for AD9889B?


  • Hi Tom,

    It would reduce noise-- it's a margin thing.  If you can meet the specifications without it then it's fine.  It's a lot easier though if you do the layout the way they did in the eval board.