We have a EVAL-ADV7391EBZ evaluation board to evaluate your video
encoder. We need to generate a R G B triple analog output (no sync signal
embedded) from your part with an input of a digital parallel input YUV 422
We would like to have your support in order to configure the ADV7391 in this
manner. Do you have some tools to generate the right set of register settings
according to the requirements of the solution which could speed up our
development or can you support us of having this set of register settings. Our
engineering team is quite new working with your part and we would like to have
your support to have it working as soon as possible and to show to our customer
that we are fulfiling their requirements with a demoboard based system.
What do you mean by "no sync signal embedded"? Do you mean no synchronization at all? What video formats are you trying to support?
There are a whole list of scripts for different situations including YCbCr 4:2:2 in and RGB out in the data sheet starting on page 92.
we are facing issue in ADV7391
ADV7391 video encoder is configured via I2C for test pattern generation and clock of 27MHz frequency is applied and Reset is kept low for 10ms and made high after that.
Test Pattern is not generated but getting a gray display. Please find the attachment of output of dac1 of ADV7391 (oscilloscope view).
The following is the configuration script used for Test Pattern Generation(NTSC).
> 1. 8'h54, 16'h1702; //RESET TO DEFAULT CONFIGURATION
> 2. 8'h54, 16'h001C; //ENABLE DAC
> 3. 8'h54, 16'h82CB; //CVBS OUT
> 4. 8'h54, 16'h8440; //TEST PATTERN ENABLE
> please let us know any changes has to be done as soon as possible
Could you please create the new thread for your query? So that it is easy to follow-up.
Please crosscheck with below writes are handled in your side.54 00 10 ; Power up 1 DAC54 01 00 ; SD only mode54 80 10 ; SSAF Luma filter enabled, NTSC mode54 82 CB ; CVBS Out out.54 87 20 ; PAL/NTSC autodetect mode enabled54 88 10 ; 10 bit input enabled54 84 40 ; SD color bar enablePlease refer here https://ez.analog.com/video/w/documents/717/adv739x-internal-color-bars-output-levels
This thread is already marked as answered. Please create new thread for new questions.It is easy to followup.
Note: When the test pattern is enabled on the ADV739X parts, they do not look at the external syncs, the timing is all generated internally.Only the pixel clock input is required.