AD8113 Reset

Hello Srivatsa,

I will need more details to determine what is causing your problem.  You mentioned "certain condition."  Please describe in detail what this condition is.  Also, where is the excess current flowing, and how much current is flowing?

Thank you.

--Jonathan

Hi Jonathan,

Please let me know if there is any timing issue using RESET and UPDATE .

Problem that we are seeing is as follows ,

Power = +/- 5V ,

IN00 - IN15 is all set to DC0V (No Signal)

When RESET and UPDATE is Asserted from L - > H there excess current Flow

Thanking you

With best regards and wishes

Hello Srivatsa,

It's important to note that the RESET feature does not reset all of the internal registers in the AD8113.  Per the block diagram shown in Figure 4, it can be seen that the RESET feature only clears the second-rank latches that determine whether or not an output is enabled or disabled.  This is most useful during power-up.  Following power-up and the assertion of RESET, the internal first-rank shift register contains random data.  If you assert UPDATE in this condition, the random data will program the switch randomly, and the supply current will correspond to the number of outputs that are enabled.  The internal shift register needs to be programmed to your desired initial state -- if you want all outputs disabled, you will have to program each output to the disabled state in either serial or parallel mode.  (Setting IN00 - IN15 to Logic 0 on power-up, RESET or UPDATE will not accomplish this -- the data must be clocked into the shift register in either serial or parallel mode.)  This procedure is described in pages 16 and 17 of the data sheet.

Best regards.

--Jonathan

Hi Jonathan,

1. Can Update and Reset be set to L at the same time .

Let me make my self clear Set IN00 - 15 to logic 0 , Apply Update L-H as per timing  Figure 1,2 based on Serial / Parallel  and then Apply Reset L -> H .

2. If so what is the min timing between Update L->H and Reset L->H after Update goes H .

Thanking you

With best regards and wishes

Hi Srivatsa,

Yes, UPDATE and RESET can be low simultaneously.  In this case, RESET overrides UPDATE, so the MSB in the second-rank latch is cleared irrespective of what is applied to the UPDATE input.  When RESET is pulled high, the UPDATE function takes over.  We don't have characterization data for the minimum wait time before pulling RESET high following UPDATE going high, but a conservative specification for this is 50 nsec.

The latch UPDATE/RESET timing itself has negligible influence on supply current.  As indicated in the previous reply, the number of enabled outputs has a proportional effect on the increase in supply current, so I would focus on that.  The shift register should be fully programmed following power-up -- either serially or in parallel -- before updating the second-rank latch.  If this is not done, the latch will contain random data, and some outputs will be enabled and others will be disabled.  Please refer to pages 16 and 17 in the data sheet for a full discussion of how to program the switch.

Best regards,

--Jonathan

Hi ,

We are seeing large current flow when we apply /RESET and /Update at the same time (L-> H).

And we need the information for min for the following :

/UPDATE______|~~~~~~~~~~~~~~~~~

/RESET ___________|~~~~~~~~~~~~

                          <---> ?ns(min)

But as you tell me that :

"We don't have characterization data for the minimum wait time before pulling RESET high following UPDATE going high, but a conservative specification for this is 50 nsec."

50 ns is it min or Typical . We need this information of min as we have decide on the timing .

We have understood the working of /UPDATE and /RESET, but by checking the data sheet and the description that you have provided we see that the min can be > 0ns what do you think .

All we want to know is the min , so that we can clear this problem .

Thanking you

With best regards and wishes

Hi ,

Can you please let me knwo with regards to this issue .

Thanking you

With best regards and wishes

Hi Srivatsa,

The 50 ns is a minimum.  As indicated in earlier responses, the excess supply current you were seeing was most likely due to the random state of the switch that occurs on power-up.

Best regards.

--Jonathan

Hi Jonathan ,

Thank you for the information with regards to this issue .

What about the following case .

OUTnn-------<==IN15==========

/REST______|~~~~~~~~~~~~~~~~~

/UPDT___________|~~~~~~~~~~~~

                    <---> ?ns(min)

Is this also 50 ns .

As there is no much details in the data sheet please let me know in details with regards to this .

Thanking you

With best regards and wishes