Hi !
I have a question about ADV7480.
Our customer connect ADV7480 after ADV7181D.
When they change NTSC<=>component, the LLC will be unstable.
I think this is OK because this happens when they change ADV7181D NTSC⇔component and frequency will change.
ADV7181D LLC output is connected to ADV7480 LLC input.
Even after Clock change to stable,ADV7480 cannot output image.
Sometime fail to output but sometime OK.
Is there a possibility that the ADV7480 hangs up or fails to output an image inside the device if a corrupted CLK is input to the LLC?
Best regards
Kawa
Hi,
Please refer here for more details https://ez.analog.com/video/w/documents/702/how-to-detect-that-the-crystal-is-working-correctly-on-the-adv7182-adv728x
And also by adjust the DLL in order to achieve the optimal data sampling scheme for your system. You can use the DR_STR, DR_STR_CLK, and DR_STR_SYNC registers to control the drive strength of LLC, and HS/VS/DE, respectively
Thanks,
Poornima
Hi
Sorry I can't understand what you are talking about.
I am not asking about XTAL.
I am talking about LLC.
When unstable LLC input to ADV7480, ADV7480 output CLK from MIPI.
DATA are all low.
After while, LLC will be stable but still MIPI DATA are low.
Is this possible? Why is it possible?
Your question is forwarded to part specialist and you will get an update soon.
Hi Kawa,
During the switch carried out in the ADV7181D, if the LLC exceeds the input specification of the ADV7481, the clock path in the ADV7481 could become unstable. It is not designed to handle clock frequencies outside the specified range.
I suggest that your customer employ more control of the LLC during the switching. Before the start of the ADV7181D switch, tri-state the LLC. After the ADV7181D switch, when everything is stable, remove the tri-state of the LLC. Your customer can also force freerun in the ADV7481 before the switch if a constant output is required.
The TRI_LLC bit in the ADV7181D is register 0x1D[7].
Best regards,
Joe
Joe-san
Thank you for your reply.
I understood.