ADV7619 I2S Audio Stream AP pin assignments

Hello Specialist,

I am implementing the schematic design for the ADV7619 part, I am very confused about the pin assignments when it is configured as I2S mode. Please help to clarify here.

  1. In your latest revision D datasheet, in the pin description on Page 12, you don't mention AP1 can be configured as I2S data. On the other hand, In Figure 5 I2S Timing, you specify the I2Sx data are distributed from AP1 to AP4. Is it a contradictory here, which one should I follow?
  2. After answering the first question, what is the first data channel? Is the audio data distributed sequentially from AP1 to AP4?
  3. I am really confused about your I2S timing diagram, it is quite different with the command standard I2S format, typically, a I2S needs a word clock.and a bit clock, are the LRCLK and SCLK in your diagram just the word clock.and bit clock respectively?
  4. Some audio chip needs to be fed a master clock, does ADV7619 need a master clock when working as the I2S mode? your Figure 5 timing diagram doesn't mention that at all. In your pin description, MCLK is an output rather than an input.
  5. What is the functionality of AP0, if I only need to support I2S, I don't need it at all, is that correct?
  6. Are the I2S modes of LEFT-JUSTIFIED and RIGHT-JUSTIFIED completely configured by I2C registers rather than physical pins?

Looking forward to your reply. Thanks.

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