I am implementing the schematic design for the ADV7619 part, I am very confused about the pin assignments when it is configured as I2S mode. Please help to clarify here.
Looking forward to your reply. Thanks.
1) In your latest revision D datasheet, in the pin description on Page 12, you don't mention AP1 can be configured as I2S data. On the other hand, In Figure 5 I2S Timing, you specify the I2Sx data are distributed from AP1 to AP4. Is it a contradictory here, which one should I follow?
As per expert comment, AP1...AP4 are the only pins that can output I2S signals.
For Page 10, Table 5, AP0, the description looks like a copy/paste typo.
2) After answering the first question, what is the first data channel? Is the audio data distributed sequentially from AP1 to AP4?
3) I am really confused about your I2S timing diagram, it is quite different with the command standard I2S format, typically, a I2S needs a word clock.and a bit clock, are the LRCLK and SCLK in your diagram just the word clock.and bit clock respectively?
Yes,Please refer here en.wikipedia.org/.../I²S
Note: 1.Bit clock lineOfficially "continuous serial clock (SCK)". Typically written "bit clock (BCLK)".2.Word clock line Officially "word select (WS)".Typically called "left-right clock (LRCLK)" or "frame sync (FS)". 0 = Left channel, 1 = Right channel
4) Some audio chip needs to be fed a master clock, does ADV7619 need a master clock when working as the I2S mode? your Figure 5 timing diagram doesn't mention that at all. In your pin description, MCLK is an output rather than an input.
Yes, ADV7619 has TMDS input,from that TMDS,audio DPLL is used to generate the internal audio master clock with a frequency of 128 times the audio sampling frequency, usually called fs.The audio master clock is used to clock the audio processing section. The ADV7619 also regenerates an audio master clock along with the extraction of the audio data.The clock regeneration is performed by an integrated DPLL.
5) Are the I2S modes of LEFT-JUSTIFIED and RIGHT-JUSTIFIED completely configured by I2C registers rather than physical pins?
Thanks for your quick response, and most questions are well answered.
I have only one question left about the MCLK. In I2S mode, it is an output rather than input. do we need to feed it with a frequency of 128fs? If yes, how should we generate this clock?
MCLK is derived from the TMDS clock and the information in the audio infoframe. For more details please refer Audio and control configuration section in ADV7619 Reference Manual.
And also the frequency of audio master clock MCLKOUT is set using the MCLK_FS_N[2:0] register,it can selects the frequency of MCLK out as multiple of 128fs.
Thanks Poornima, as far as I understand from your enlightenment, if I only need to support 4 channels of audio data under I2S mode, the minimum IO number I need is 6, the pins needed are AP1~AP5 and SCLK. AP0 is not involved, and MCLK is not mandatory provided that I can latch the data by using SCLK and LRCLK only. Is that right?
Hi,Yes.LRCLK signal is available on the AP5 pin.I2Sx((WHERE x = 0, 1, 2, OR 3) signals are available on the following pins:AP1,AP2,AP3 and AP4.
Sorry for bothering you again. I just came across another pin description of audio pin assignments in your UG-237. On Page 13, it says that 5 pins from AP0 to AP4 can be configured as I2S, it contradicts with your datasheet description again. Can you help to confirm how many channels of I2S audio ADV7619 supports and how they are distributed. Look forward to your double confirmation urgently. Thanks.
ADV7619 supports 8 channels of uncompressed audio (Front Left, Front Right, Center, LFE, Left Surround, Right Surround, Left Rear Surround, Right Rear Surround) using 4 data pins. Each data pin contains two channels of audio.
There is a typo mistake between datasheet and reference manual.Expert answered in this thread, Please refer here https://ez.analog.com/video/f/q-a/7160/adv7619-i2s-audio-stream-ap-pins