port blimp's osd onto the arm board

I want to port blimp's osd onto the arm board, do you have specific instructions

Parents
  • 0
    •  Analog Employees 
    on Mar 29, 2019 9:17 AM over 1 year ago

    Hi,

    You have the OSD API functions in Blimp_ADV7625_Framework_User_Manual.pdf. Please refer here https://ez.analog.com/video/w/documents/707/blimp-osd-designer-tool-for-naturevue-adv800x-and-advantiv-adv7625

     Do you have one of our evaluation board? If so,load our application binary,there you have the inbuilt demo OSD at https://ez.analog.com/video/w/documents/698/advantiv-eval-adv7625-smz-video-evaluation-board

    And also it seems like duplicate of this thread at ez.analog.com/.../adv7625-ported-to-arm-board

    Please do not create duplicate thread since it would be difficult for tracking.

    Thanks very much for understanding.

    Thanks,

    Poornima

  • Sorry, I just want people to answer my question as soon as possible, so I made two posts

    Thank you very much for your reply.

  • HI;

    Do you have any experience of successfully porting to the arm board?Can you give me a demo?Let me see how you implement osd display。

    thanks

    sylon

  • +1
    •  Analog Employees 
    on Apr 8, 2019 9:21 AM over 1 year ago in reply to sylon

    Hi,

    When I have blocked SpiTransfer function, it can still be displayed correctly after burning it.

                  Are you saying, removing SPI flash from eval board as well as commenting out the SPI transfer function right? Can you share the details what are commented from code( source filename and APIs etc)?

    Drag in six labels, change the memory option to internal storage, and change the resolution to the current resolution.Then the TV will display the six labels correctly.

                 We assume that this statement is for Eval board, Is it right?

    Do you have any experience of successfully porting to the arm board?Can you give me a demo?Let me see how you implement osd display.

                 Please refer Advantiv_CrossPoint_Application_Userguide Appendix A which explains  OSD integration with HDMI driver code which is available at ADV7625 ADV7626 ADV7627 evaluation board software package documents. This document explains for Blackfin based eval board with VDSP. The same way you can integrate for ARM also. Please let us know if any issues?

    Thanks,

    Poornima

  • hello;

    1、My spi function is empty, as shown in the figure below

    • 2、yes,All operations are on the eval board
    • 3、I looked at the data that you gave me, but there was very little information on the transplant part.
  • 0
    •  Analog Employees 
    on Apr 8, 2019 11:24 AM over 1 year ago in reply to sylon

    Hi,

    Thank you for the details. We will check the same.

    For 1 and 2, What is software version you are using? Can you send the log file snippet for the same?

    Thanks,

    Poornima

  • Hi,Poornima

    This is my log file

    teraterm.log
    �
    
    U-Boot 2012.07-rc2 (ADI-2012R2) (Jul 01 2013 - 15:24:32)
    
    CPU:   ADSP bf524-0.2 (Detected Rev: 0.2) (spi flash boot)
    Board: ADI Advantiv? Video Evaluation Board
           Support: http://ez.analog.com 
    Clock: VCO: 300 MHz, Core: 300 MHz, System: 100 MHz
    RAM:   8 MiB
    SF: Detected M25P80 with page size 64 KiB, total 1 MiB
    *** Warning - bad CRC, using default environment
    
    In:    serial
    Out:   serial
    Err:   serial
    KGDB:  [on serial] ready
    Hit any key to stop autoboot:  5  4  3  2  1  0 
    SF: Detected M25P80 with page size 64 KiB, total 1 MiB
    ## Booting ldr image at 0x00100000 ...
    
    
    Advantiv Video Evaluation Board Software Version: 2.4.-8376108 
    
    Heap Space: 358368 bytes free
    Diagnostic Interface set to UART.
    Initializing USB...Successful.  Waiting for USB Host
    7625_CSN set to 0.
    BF_7625_RESETn set to 1.
    
    ********************************************************************
      ADI X-Point Repeater Application Ver X2.4REL
      PLATFORM: PAVPipe Revision 1 Rev 0x1
      HDMI-RX:  ADV7625 Rev 0x4082
      HDMI-TX:  ADV7625 Rev 0x4082
      Created:  Apr  3 2019 At 09:35:54
    ********************************************************************
    
    REP: Driver Enabled
    Starting Repeater on Boot ...
    Setting I2C Addressing
    RX: BSTATUS Set to 0
    -T1: 06:677 #### Muted using: TMDS BLKOUT ASP (TX PLL not locked)
    -T1: 06:703 Setting audio parameters:
                 SF=32 KHz  CC=2  HBR=No
    Setting I2C Addressing
    RX: BSTATUS Set to 0
    -T2: 07:068 #### Muted using: TMDS BLKOUT ASP (TX PLL not locked)
    -T2: 07:093 Setting audio parameters:
                 SF=32 KHz  CC=2  HBR=No
    XREP:Updating Routing : XREP_NONE,XREP_NONE,
    XREP: Audio Pass-through Enabled on Repeater Path: 0
    XREP:Updating Routing :  sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    -R1: 07:396 @@@@ RX Mute State changed to 2 
    APP: Freerun is ON. VIC is 2
    -R1: 07:407 Configuring Sync Polarity. H: 0, V: 0 
    -R1: 07:410 @@@@ RX entering free-run
    -R1: 07:410 @@@@ RX started delay to unmute
    sylon debug:ADIAPI_OsdConInit  1195 
    OSDAPI_OSDApiInit: Initialization is done. 
    
    Virtual memory used size is (in bytes) 0
    
    -OSD 07:530 666666666666666666666
    -OSD 07:580 Adjusted OSD resolutionto 720x480 Osd3DFmt 0
    -R1: 07:583 @@@@ RX Mute State changed to 0 
    -R1: 07:583 @@@@ RX unmute delay expired
    HDMI Port A->HDMI Tx A,  sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    -R2: 07:718 @@@@ RX Mute State changed to 2 
    APP: Freerun is ON. VIC is 2
    -R2: 07:728 Configuring Sync Polarity. H: 0, V: 0 
    -R2: 07:731 @@@@ RX entering free-run
    -R2: 07:731 @@@@ RX started delay to unmute
    HDMI Port B->HDMI Tx B, 
    XREP: Output 0 -> HDMI REP 
     XREP: Output 1 -> HDMI REP 
     XREP: Splitter Mode:  FALSE  
     route a txa
    XREP:Updating Routing : Port A already selected for txa
    Command execution failed
    route b txb
    XREP:Updating Routing : Port B already selected for txb
    Command execution failed
    >-T1: 07:794 HPD changed to LOW
    -T1: 07:805 #### Muted using: TMDS BLKOUT ASP (TX PLL not locked)
    -T1: 07:830 Setting audio parameters:
                 SF=32 KHz  CC=2  HBR=No
    All TX HPDs are low..Writing Default EDID
    -T1: 07:833 ### An empty EDID was received due to HPD = 0 and hence default EDID is sent to the corresponding source ###
    -R1: 07:834 Processing TXPKT New EDID on Repeater: 0
    APP: EDID received. Setting HPD to LOW on Port A
    APP: Writing Default EDID to Primary EDID space for Port A!!..
    ------------------------- EDID BLOCK 0 -------------------------
    Edid Version 1.3
    Mon Timing:
        Pixel clock = 148.50 MHz
        H Active    = 1920
        V Active    = 1080
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1280
        V Active    = 720
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Name:   ADI HDMI
        
    
    Mon Freq:
        Min V Freq = 29 Hz
        Max V Freq = 86 Hz
        Min H Freq = 15 KHz
        Max H Freq = 111 KHz
        Max Pixel Clk Rate = 300 MHz
    Edid extensions blocks: 1
    
    ========================= EDID BLOCK 1 =========================
    CEA extension block revision 3
    Underscan=Yes  Audio=Yes  YCbCr4:4:4=Yes  YCbCr4:2:2=Yes
    Data block collection information:
        Video data block
            VIC=16
            VIC=1
            VIC=3
            VIC=4
            VIC=5
            VIC=7
            VIC=18
            VIC=19
            VIC=20
            VIC=22
            VIC=31
            VIC=32
            VIC=93
            VIC=94
            VIC=95
            VIC=98
            VIC=99
            VIC=100
        Audio data block
           Format Code          = 1 (Linear PCM)
            Max. No. of Channels= 8
            Sampling Freq. (KHz)= 32  44.1  48  88.2  96  176.4  192
            Length (bits)       = 16  20  24
        Speaker allocation data block
           0xff
           0x07
           0x00
        VSDB data block
           30-bit Deep color (RGB)
           36-bit Deep color (RGB)
           YCbCr Deep color supported
           Max TMDS clock = 300 MHz
           Content Type: Graphics (CNC0)
           Content Type: Photo    (CNC1)
           Content Type: Cinema   (CNC2)
           Content Type: Game     (CNC3)
           3D_present = 1, 3D_multi_present = 0, HDMI_VIC_LEN = 4, HDMI_3D_LEN = 0
           HDMI Sink supports 3D  with only mandatory 3D formats
           HDMI_VIC_1  = 0x1
           HDMI_VIC_2  = 0x2
           HDMI_VIC_3  = 0x3
           HDMI_VIC_4  = 0x4
        Extended Tag data block
           Extended tag code is 14
           YCbCr 4:2:0 Video Data Block (Y420VDB) 
              VIC=96
              VIC=97
              VIC=101
              VIC=102
              VIC=106
              VIC=107
    SPA location is at 0xa3, SPA = 1.0.0.0
    Mon Timing:
        Pixel clock = 27.0 MHz
        H Active    = 720
        V Active    = 576
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 27.0 MHz
        H Active    = 720
        V Active    = 480
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1920
        V Active    = 540
        Interlaced
        No stereo
        Separate sync = 3
        +ve VSync
        +ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1280
        V Active    = 720
        Progressive
        No stereo
        Separate sync = 3
        +ve VSync
        +ve HSync
    ########################### EDID END ###########################
    
    APP: Downstream Connection SPA  is  1.0.0.0
    APP: Upstream Port 0 SPA is 1.1.0.0
    APP: Upstream Port 1 SPA is 1.2.0.0
    APP: Upstream Port 2 SPA is 1.3.0.0
    APP: Upstream Port 3 SPA is 1.4.0.0
    APP: Upstream Port 4 SPA is 1.5.0.0
    APP: SPA Offset Detected as 0xa3
    -T1: 07:933 MSEN changed to LOW
    -T2: 07:938 HPD changed to LOW
    -T2: 07:948 #### Muted using: TMDS BLKOUT ASP (TX PLL not locked)
    -T2: 07:973 Setting audio parameters:
                 SF=32 KHz  CC=2  HBR=No
    All TX HPDs are low..Writing Default EDID
    -T2: 07:977 ### An empty EDID was received due to HPD = 0 and hence default EDID is sent to the corresponding source ###
    -R2: 07:977 Processing TXPKT New EDID on Repeater: 1
    APP: EDID received. Setting HPD to LOW on Port B
    APP: Writing Default EDID to Secondary EDID space for Port B!!..
    ------------------------- EDID BLOCK 0 -------------------------
    Edid Version 1.3
    Mon Timing:
        Pixel clock = 148.50 MHz
        H Active    = 1920
        V Active    = 1080
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1280
        V Active    = 720
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Name:   ADI HDMI
        
    
    Mon Freq:
        Min V Freq = 29 Hz
        Max V Freq = 86 Hz
        Min H Freq = 15 KHz
        Max H Freq = 111 KHz
        Max Pixel Clk Rate = 300 MHz
    Edid extensions blocks: 1
    
    ========================= EDID BLOCK 1 =========================
    CEA extension block revision 3
    Underscan=Yes  Audio=Yes  YCbCr4:4:4=Yes  YCbCr4:2:2=Yes
    Data block collection information:
        Video data block
            VIC=16
            VIC=1
            VIC=3
            VIC=4
            VIC=5
            VIC=7
            VIC=18
            VIC=19
            VIC=20
            VIC=22
            VIC=31
            VIC=32
            VIC=93
            VIC=94
            VIC=95
            VIC=98
            VIC=99
            VIC=100
        Audio data block
           Format Code          = 1 (Linear PCM)
            Max. No. of Channels= 8
            Sampling Freq. (KHz)= 32  44.1  48  88.2  96  176.4  192
            Length (bits)       = 16  20  24
        Speaker allocation data block
           0xff
           0x07
           0x00
        VSDB data block
           30-bit Deep color (RGB)
           36-bit Deep color (RGB)
           YCbCr Deep color supported
           Max TMDS clock = 300 MHz
           Content Type: Graphics (CNC0)
           Content Type: Photo    (CNC1)
           Content Type: Cinema   (CNC2)
           Content Type: Game     (CNC3)
           3D_present = 1, 3D_multi_present = 0, HDMI_VIC_LEN = 4, HDMI_3D_LEN = 0
           HDMI Sink supports 3D  with only mandatory 3D formats
           HDMI_VIC_1  = 0x1
           HDMI_VIC_2  = 0x2
           HDMI_VIC_3  = 0x3
           HDMI_VIC_4  = 0x4
        Extended Tag data block
           Extended tag code is 14
           YCbCr 4:2:0 Video Data Block (Y420VDB) 
              VIC=96
              VIC=97
              VIC=101
              VIC=102
              VIC=106
              VIC=107
    SPA location is at 0xa3, SPA = 1.0.0.0
    Mon Timing:
        Pixel clock = 27.0 MHz
        H Active    = 720
        V Active    = 576
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 27.0 MHz
        H Active    = 720
        V Active    = 480
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1920
        V Active    = 540
        Interlaced
        No stereo
        Separate sync = 3
        +ve VSync
        +ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1280
        V Active    = 720
        Progressive
        No stereo
        Separate sync = 3
        +ve VSync
        +ve HSync
    ########################### EDID END ###########################
    
    APP: Downstream Connection SPA  is  1.0.0.0
    APP: Upstream Port 0 SPA is 1.1.0.0
    APP: Upstream Port 1 SPA is 1.2.0.0
    APP: Upstream Port 2 SPA is 1.3.0.0
    APP: Upstream Port 3 SPA is 1.4.0.0
    APP: Upstream Port 4 SPA is 1.5.0.0
    APP: SPA Offset Detected as 0xa3
    -T2: 08:078 MSEN changed to LOW
    -R1: 08:088 Bcaps/Bstatus changed. Hdcp reset required
    RX: BSTATUS Set to 101
    -R1: 08:092 HDCP setting change: BCAPS=0xc0  Bstatus=0x101
    -R1: 08:098 TMDS Clock  NOT  detected on selected port (A)
    -R1: 08:098 Resetting BKSV Waiting Status to 0 due to TMDS Change
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    APP: Freerun is ON. VIC is 2
    -R1: 08:109 Configuring Sync Polarity. H: 0, V: 0 
    -R1: 08:112 @@@@ RX entering free-run
    sylon debug:ADIAPI_OsdConInit  1195 
    -R1: 08:127 Resetting BKSV Waiting Status to 0 due to TMDS Change
    -R1: 08:128 Resetting BKSV Waiting Status to 0 due to TMDS Change
    -R1: 08:128 Resetting BKSV Waiting Status to 0 due to TMDS Change
    RX: BSTATUS Set to 101
    -R1: 08:130 Source signal changed to DVI
    -R1: 08:130 Received AVI Info Frame (RAW) Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
    -R1: 08:132 Configuring Sync Polarity. H: 0, V: 0 
    -R1: 08:133 Received AVI Info Frame Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
                 VIC = 2 (720x480p @ 60Hz)
                 Colorspace = RGB      PR = 0
    -R2: 08:152 @@@@ RX Mute State changed to 0 
    -R2: 08:152 @@@@ RX unmute delay expired
    -R2: 08:160 Bcaps/Bstatus changed. Hdcp reset required
    RX: BSTATUS Set to 101
    -R2: 08:164 HDCP setting change: BCAPS=0xc0  Bstatus=0x101
    -R2: 08:169 TMDS Clock  NOT  detected on selected port (B)
    -R2: 08:169 Resetting BKSV Waiting Status to 0 due to TMDS Change
    -R2: 08:169 Resetting BKSV Waiting Status to 0 due to TMDS Change
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    APP: Freerun is ON. VIC is 2
    -R2: 08:180 Configuring Sync Polarity. H: 0, V: 0 
    -R2: 08:183 @@@@ RX entering free-run
    -R2: 08:197 Resetting BKSV Waiting Status to 0 due to TMDS Change
    -R2: 08:198 Resetting BKSV Waiting Status to 0 due to TMDS Change
    RX: BSTATUS Set to 101
    -R2: 08:200 Source signal changed to DVI
    -R2: 08:200 Received AVI Info Frame (RAW) Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
    -R2: 08:201 Configuring Sync Polarity. H: 0, V: 0 
    -R2: 08:203 Received AVI Info Frame Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
                 VIC = 2 (720x480p @ 60Hz)
                 Colorspace = RGB      PR = 0
    XREP:: Changed system mode to Disconnected
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    -R1: 08:331 Configuring Sync Polarity. H: 0, V: 0 
    -R1: 08:335 @@@@ RX Mute State changed to 2 
    APP: Freerun is OFF
    -R1: 08:345 ----------> Int: AVI+
    XREP:: Changed system mode to Disconnected
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    -R2: 08:363 Configuring Sync Polarity. H: 0, V: 0 
    -R2: 08:367 @@@@ RX Mute State changed to 2 
    APP: Freerun is OFF
    -R2: 08:377 ----------> Int: AVI+
    -R1: 08:390 Bcaps/Bstatus changed. Hdcp reset required
    RX: BSTATUS Set to 0
    -R1: 08:394 HDCP setting change: BCAPS=0x80  Bstatus=0x0
    -R1: 08:400 Received AVI Info Frame (RAW) Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
    -R1: 08:402 Configuring Sync Polarity. H: 0, V: 0 
    -R1: 08:404 Received AVI Info Frame Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
                 VIC = 2 (720x480p @ 60Hz)
                 Colorspace = RGB      PR = 0
    -R2: 08:430 Bcaps/Bstatus changed. Hdcp reset required
    RX: BSTATUS Set to 0
    -R2: 08:434 HDCP setting change: BCAPS=0x80  Bstatus=0x0
    -R2: 08:441 Received AVI Info Frame (RAW) Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
    -R2: 08:443 Configuring Sync Polarity. H: 0, V: 0 
    -R2: 08:444 Received AVI Info Frame Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
                 VIC = 2 (720x480p @ 60Hz)
                 Colorspace = RGB      PR = 0
    APP: De-assert Done! Setting port A  HPD to HI.
    -R2: 08:596 ----------> Int: Port A TMDS=0   1
    -R2: 08:603 Resetting BKSV Waiting Status to 0 due to TMDS Change
    -R1: 08:662 TMDS Clock  NOT  detected on selected port (A)
    -R1: 08:662 Resetting BKSV Waiting Status to 0 due to TMDS Change
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    -R1: 08:669 Configuring Sync Polarity. H: 0, V: 0 
    APP: Freerun is OFF
    APP: De-assert Done! Setting port B  HPD to HI.
    

    Would you get the same results if you tried it the way I said?

    Looking forward to your reply. Thank you

    sylon

Reply
  • Hi,Poornima

    This is my log file

    teraterm.log
    �
    
    U-Boot 2012.07-rc2 (ADI-2012R2) (Jul 01 2013 - 15:24:32)
    
    CPU:   ADSP bf524-0.2 (Detected Rev: 0.2) (spi flash boot)
    Board: ADI Advantiv? Video Evaluation Board
           Support: http://ez.analog.com 
    Clock: VCO: 300 MHz, Core: 300 MHz, System: 100 MHz
    RAM:   8 MiB
    SF: Detected M25P80 with page size 64 KiB, total 1 MiB
    *** Warning - bad CRC, using default environment
    
    In:    serial
    Out:   serial
    Err:   serial
    KGDB:  [on serial] ready
    Hit any key to stop autoboot:  5  4  3  2  1  0 
    SF: Detected M25P80 with page size 64 KiB, total 1 MiB
    ## Booting ldr image at 0x00100000 ...
    
    
    Advantiv Video Evaluation Board Software Version: 2.4.-8376108 
    
    Heap Space: 358368 bytes free
    Diagnostic Interface set to UART.
    Initializing USB...Successful.  Waiting for USB Host
    7625_CSN set to 0.
    BF_7625_RESETn set to 1.
    
    ********************************************************************
      ADI X-Point Repeater Application Ver X2.4REL
      PLATFORM: PAVPipe Revision 1 Rev 0x1
      HDMI-RX:  ADV7625 Rev 0x4082
      HDMI-TX:  ADV7625 Rev 0x4082
      Created:  Apr  3 2019 At 09:35:54
    ********************************************************************
    
    REP: Driver Enabled
    Starting Repeater on Boot ...
    Setting I2C Addressing
    RX: BSTATUS Set to 0
    -T1: 06:677 #### Muted using: TMDS BLKOUT ASP (TX PLL not locked)
    -T1: 06:703 Setting audio parameters:
                 SF=32 KHz  CC=2  HBR=No
    Setting I2C Addressing
    RX: BSTATUS Set to 0
    -T2: 07:068 #### Muted using: TMDS BLKOUT ASP (TX PLL not locked)
    -T2: 07:093 Setting audio parameters:
                 SF=32 KHz  CC=2  HBR=No
    XREP:Updating Routing : XREP_NONE,XREP_NONE,
    XREP: Audio Pass-through Enabled on Repeater Path: 0
    XREP:Updating Routing :  sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    -R1: 07:396 @@@@ RX Mute State changed to 2 
    APP: Freerun is ON. VIC is 2
    -R1: 07:407 Configuring Sync Polarity. H: 0, V: 0 
    -R1: 07:410 @@@@ RX entering free-run
    -R1: 07:410 @@@@ RX started delay to unmute
    sylon debug:ADIAPI_OsdConInit  1195 
    OSDAPI_OSDApiInit: Initialization is done. 
    
    Virtual memory used size is (in bytes) 0
    
    -OSD 07:530 666666666666666666666
    -OSD 07:580 Adjusted OSD resolutionto 720x480 Osd3DFmt 0
    -R1: 07:583 @@@@ RX Mute State changed to 0 
    -R1: 07:583 @@@@ RX unmute delay expired
    HDMI Port A->HDMI Tx A,  sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    -R2: 07:718 @@@@ RX Mute State changed to 2 
    APP: Freerun is ON. VIC is 2
    -R2: 07:728 Configuring Sync Polarity. H: 0, V: 0 
    -R2: 07:731 @@@@ RX entering free-run
    -R2: 07:731 @@@@ RX started delay to unmute
    HDMI Port B->HDMI Tx B, 
    XREP: Output 0 -> HDMI REP 
     XREP: Output 1 -> HDMI REP 
     XREP: Splitter Mode:  FALSE  
     route a txa
    XREP:Updating Routing : Port A already selected for txa
    Command execution failed
    route b txb
    XREP:Updating Routing : Port B already selected for txb
    Command execution failed
    >-T1: 07:794 HPD changed to LOW
    -T1: 07:805 #### Muted using: TMDS BLKOUT ASP (TX PLL not locked)
    -T1: 07:830 Setting audio parameters:
                 SF=32 KHz  CC=2  HBR=No
    All TX HPDs are low..Writing Default EDID
    -T1: 07:833 ### An empty EDID was received due to HPD = 0 and hence default EDID is sent to the corresponding source ###
    -R1: 07:834 Processing TXPKT New EDID on Repeater: 0
    APP: EDID received. Setting HPD to LOW on Port A
    APP: Writing Default EDID to Primary EDID space for Port A!!..
    ------------------------- EDID BLOCK 0 -------------------------
    Edid Version 1.3
    Mon Timing:
        Pixel clock = 148.50 MHz
        H Active    = 1920
        V Active    = 1080
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1280
        V Active    = 720
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Name:   ADI HDMI
        
    
    Mon Freq:
        Min V Freq = 29 Hz
        Max V Freq = 86 Hz
        Min H Freq = 15 KHz
        Max H Freq = 111 KHz
        Max Pixel Clk Rate = 300 MHz
    Edid extensions blocks: 1
    
    ========================= EDID BLOCK 1 =========================
    CEA extension block revision 3
    Underscan=Yes  Audio=Yes  YCbCr4:4:4=Yes  YCbCr4:2:2=Yes
    Data block collection information:
        Video data block
            VIC=16
            VIC=1
            VIC=3
            VIC=4
            VIC=5
            VIC=7
            VIC=18
            VIC=19
            VIC=20
            VIC=22
            VIC=31
            VIC=32
            VIC=93
            VIC=94
            VIC=95
            VIC=98
            VIC=99
            VIC=100
        Audio data block
           Format Code          = 1 (Linear PCM)
            Max. No. of Channels= 8
            Sampling Freq. (KHz)= 32  44.1  48  88.2  96  176.4  192
            Length (bits)       = 16  20  24
        Speaker allocation data block
           0xff
           0x07
           0x00
        VSDB data block
           30-bit Deep color (RGB)
           36-bit Deep color (RGB)
           YCbCr Deep color supported
           Max TMDS clock = 300 MHz
           Content Type: Graphics (CNC0)
           Content Type: Photo    (CNC1)
           Content Type: Cinema   (CNC2)
           Content Type: Game     (CNC3)
           3D_present = 1, 3D_multi_present = 0, HDMI_VIC_LEN = 4, HDMI_3D_LEN = 0
           HDMI Sink supports 3D  with only mandatory 3D formats
           HDMI_VIC_1  = 0x1
           HDMI_VIC_2  = 0x2
           HDMI_VIC_3  = 0x3
           HDMI_VIC_4  = 0x4
        Extended Tag data block
           Extended tag code is 14
           YCbCr 4:2:0 Video Data Block (Y420VDB) 
              VIC=96
              VIC=97
              VIC=101
              VIC=102
              VIC=106
              VIC=107
    SPA location is at 0xa3, SPA = 1.0.0.0
    Mon Timing:
        Pixel clock = 27.0 MHz
        H Active    = 720
        V Active    = 576
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 27.0 MHz
        H Active    = 720
        V Active    = 480
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1920
        V Active    = 540
        Interlaced
        No stereo
        Separate sync = 3
        +ve VSync
        +ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1280
        V Active    = 720
        Progressive
        No stereo
        Separate sync = 3
        +ve VSync
        +ve HSync
    ########################### EDID END ###########################
    
    APP: Downstream Connection SPA  is  1.0.0.0
    APP: Upstream Port 0 SPA is 1.1.0.0
    APP: Upstream Port 1 SPA is 1.2.0.0
    APP: Upstream Port 2 SPA is 1.3.0.0
    APP: Upstream Port 3 SPA is 1.4.0.0
    APP: Upstream Port 4 SPA is 1.5.0.0
    APP: SPA Offset Detected as 0xa3
    -T1: 07:933 MSEN changed to LOW
    -T2: 07:938 HPD changed to LOW
    -T2: 07:948 #### Muted using: TMDS BLKOUT ASP (TX PLL not locked)
    -T2: 07:973 Setting audio parameters:
                 SF=32 KHz  CC=2  HBR=No
    All TX HPDs are low..Writing Default EDID
    -T2: 07:977 ### An empty EDID was received due to HPD = 0 and hence default EDID is sent to the corresponding source ###
    -R2: 07:977 Processing TXPKT New EDID on Repeater: 1
    APP: EDID received. Setting HPD to LOW on Port B
    APP: Writing Default EDID to Secondary EDID space for Port B!!..
    ------------------------- EDID BLOCK 0 -------------------------
    Edid Version 1.3
    Mon Timing:
        Pixel clock = 148.50 MHz
        H Active    = 1920
        V Active    = 1080
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1280
        V Active    = 720
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Name:   ADI HDMI
        
    
    Mon Freq:
        Min V Freq = 29 Hz
        Max V Freq = 86 Hz
        Min H Freq = 15 KHz
        Max H Freq = 111 KHz
        Max Pixel Clk Rate = 300 MHz
    Edid extensions blocks: 1
    
    ========================= EDID BLOCK 1 =========================
    CEA extension block revision 3
    Underscan=Yes  Audio=Yes  YCbCr4:4:4=Yes  YCbCr4:2:2=Yes
    Data block collection information:
        Video data block
            VIC=16
            VIC=1
            VIC=3
            VIC=4
            VIC=5
            VIC=7
            VIC=18
            VIC=19
            VIC=20
            VIC=22
            VIC=31
            VIC=32
            VIC=93
            VIC=94
            VIC=95
            VIC=98
            VIC=99
            VIC=100
        Audio data block
           Format Code          = 1 (Linear PCM)
            Max. No. of Channels= 8
            Sampling Freq. (KHz)= 32  44.1  48  88.2  96  176.4  192
            Length (bits)       = 16  20  24
        Speaker allocation data block
           0xff
           0x07
           0x00
        VSDB data block
           30-bit Deep color (RGB)
           36-bit Deep color (RGB)
           YCbCr Deep color supported
           Max TMDS clock = 300 MHz
           Content Type: Graphics (CNC0)
           Content Type: Photo    (CNC1)
           Content Type: Cinema   (CNC2)
           Content Type: Game     (CNC3)
           3D_present = 1, 3D_multi_present = 0, HDMI_VIC_LEN = 4, HDMI_3D_LEN = 0
           HDMI Sink supports 3D  with only mandatory 3D formats
           HDMI_VIC_1  = 0x1
           HDMI_VIC_2  = 0x2
           HDMI_VIC_3  = 0x3
           HDMI_VIC_4  = 0x4
        Extended Tag data block
           Extended tag code is 14
           YCbCr 4:2:0 Video Data Block (Y420VDB) 
              VIC=96
              VIC=97
              VIC=101
              VIC=102
              VIC=106
              VIC=107
    SPA location is at 0xa3, SPA = 1.0.0.0
    Mon Timing:
        Pixel clock = 27.0 MHz
        H Active    = 720
        V Active    = 576
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 27.0 MHz
        H Active    = 720
        V Active    = 480
        Progressive
        No stereo
        Separate sync = 3
        -ve Vsync
        -ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1920
        V Active    = 540
        Interlaced
        No stereo
        Separate sync = 3
        +ve VSync
        +ve HSync
    Mon Timing:
        Pixel clock = 74.25 MHz
        H Active    = 1280
        V Active    = 720
        Progressive
        No stereo
        Separate sync = 3
        +ve VSync
        +ve HSync
    ########################### EDID END ###########################
    
    APP: Downstream Connection SPA  is  1.0.0.0
    APP: Upstream Port 0 SPA is 1.1.0.0
    APP: Upstream Port 1 SPA is 1.2.0.0
    APP: Upstream Port 2 SPA is 1.3.0.0
    APP: Upstream Port 3 SPA is 1.4.0.0
    APP: Upstream Port 4 SPA is 1.5.0.0
    APP: SPA Offset Detected as 0xa3
    -T2: 08:078 MSEN changed to LOW
    -R1: 08:088 Bcaps/Bstatus changed. Hdcp reset required
    RX: BSTATUS Set to 101
    -R1: 08:092 HDCP setting change: BCAPS=0xc0  Bstatus=0x101
    -R1: 08:098 TMDS Clock  NOT  detected on selected port (A)
    -R1: 08:098 Resetting BKSV Waiting Status to 0 due to TMDS Change
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    APP: Freerun is ON. VIC is 2
    -R1: 08:109 Configuring Sync Polarity. H: 0, V: 0 
    -R1: 08:112 @@@@ RX entering free-run
    sylon debug:ADIAPI_OsdConInit  1195 
    -R1: 08:127 Resetting BKSV Waiting Status to 0 due to TMDS Change
    -R1: 08:128 Resetting BKSV Waiting Status to 0 due to TMDS Change
    -R1: 08:128 Resetting BKSV Waiting Status to 0 due to TMDS Change
    RX: BSTATUS Set to 101
    -R1: 08:130 Source signal changed to DVI
    -R1: 08:130 Received AVI Info Frame (RAW) Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
    -R1: 08:132 Configuring Sync Polarity. H: 0, V: 0 
    -R1: 08:133 Received AVI Info Frame Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
                 VIC = 2 (720x480p @ 60Hz)
                 Colorspace = RGB      PR = 0
    -R2: 08:152 @@@@ RX Mute State changed to 0 
    -R2: 08:152 @@@@ RX unmute delay expired
    -R2: 08:160 Bcaps/Bstatus changed. Hdcp reset required
    RX: BSTATUS Set to 101
    -R2: 08:164 HDCP setting change: BCAPS=0xc0  Bstatus=0x101
    -R2: 08:169 TMDS Clock  NOT  detected on selected port (B)
    -R2: 08:169 Resetting BKSV Waiting Status to 0 due to TMDS Change
    -R2: 08:169 Resetting BKSV Waiting Status to 0 due to TMDS Change
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    APP: Freerun is ON. VIC is 2
    -R2: 08:180 Configuring Sync Polarity. H: 0, V: 0 
    -R2: 08:183 @@@@ RX entering free-run
    -R2: 08:197 Resetting BKSV Waiting Status to 0 due to TMDS Change
    -R2: 08:198 Resetting BKSV Waiting Status to 0 due to TMDS Change
    RX: BSTATUS Set to 101
    -R2: 08:200 Source signal changed to DVI
    -R2: 08:200 Received AVI Info Frame (RAW) Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
    -R2: 08:201 Configuring Sync Polarity. H: 0, V: 0 
    -R2: 08:203 Received AVI Info Frame Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
                 VIC = 2 (720x480p @ 60Hz)
                 Colorspace = RGB      PR = 0
    XREP:: Changed system mode to Disconnected
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    -R1: 08:331 Configuring Sync Polarity. H: 0, V: 0 
    -R1: 08:335 @@@@ RX Mute State changed to 2 
    APP: Freerun is OFF
    -R1: 08:345 ----------> Int: AVI+
    XREP:: Changed system mode to Disconnected
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    -R2: 08:363 Configuring Sync Polarity. H: 0, V: 0 
    -R2: 08:367 @@@@ RX Mute State changed to 2 
    APP: Freerun is OFF
    -R2: 08:377 ----------> Int: AVI+
    -R1: 08:390 Bcaps/Bstatus changed. Hdcp reset required
    RX: BSTATUS Set to 0
    -R1: 08:394 HDCP setting change: BCAPS=0x80  Bstatus=0x0
    -R1: 08:400 Received AVI Info Frame (RAW) Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
    -R1: 08:402 Configuring Sync Polarity. H: 0, V: 0 
    -R1: 08:404 Received AVI Info Frame Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
                 VIC = 2 (720x480p @ 60Hz)
                 Colorspace = RGB      PR = 0
    -R2: 08:430 Bcaps/Bstatus changed. Hdcp reset required
    RX: BSTATUS Set to 0
    -R2: 08:434 HDCP setting change: BCAPS=0x80  Bstatus=0x0
    -R2: 08:441 Received AVI Info Frame (RAW) Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
    -R2: 08:443 Configuring Sync Polarity. H: 0, V: 0 
    -R2: 08:444 Received AVI Info Frame Packet:
                 02 02 0d 00 08 00 02 00   00 00 00 00 00 00 00 00
                 VIC = 2 (720x480p @ 60Hz)
                 Colorspace = RGB      PR = 0
    APP: De-assert Done! Setting port A  HPD to HI.
    -R2: 08:596 ----------> Int: Port A TMDS=0   1
    -R2: 08:603 Resetting BKSV Waiting Status to 0 due to TMDS Change
    -R1: 08:662 TMDS Clock  NOT  detected on selected port (A)
    -R1: 08:662 Resetting BKSV Waiting Status to 0 due to TMDS Change
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
     sylon debug : ****************ProcessFreeRun ###################
    -R1: 08:669 Configuring Sync Polarity. H: 0, V: 0 
    APP: Freerun is OFF
    APP: De-assert Done! Setting port B  HPD to HI.
    

    Would you get the same results if you tried it the way I said?

    Looking forward to your reply. Thank you

    sylon

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