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AD9983A noise

we have a vision system which is able to interface up to six
black&white analog industrial cameras.

Each camera in connected to one of the three primary
input of the ADC AD9983A. The secondary inputs are not used then tied to the
ground through a 75Ohm resistor.

We’re using the internal PLL to generate a clock synchronized with the
incoming video. The pixel clock is around 30MHz

. The ADC is configured in 4:4:4 mode, no DDR. ADC power supplies are
generated from a +5V power supply, through several low noise LDO.

The converted video from the “Red” and “Green” are OK, but the “Blue” channel is not OK, we have a
spatial noise on one pixel on two, each line, that could be seen on the
Channel3_noise.jpg image. There is a difference of 5 to 6 LSB between
contiguous pixels…which seems to be independent of the pixel values.

As I said before, we have two AD9983A ADCs on each board, and the
problem is observed on both “blue” channels. It is also seen on several boards.

The ADC internal register configuration is in here

00 - ChipRevision       : 00    

   01 - PllDivMsb          : 3b    

   02 - PllDivLsb          : 00    

   03 - VcoCpmp            : 60    

   04 - PhaseAdjust        : 80    

   05 - Gain[R][0]         : 40    

   06 - Gain[R][1]         : 00    

   07 - Gain[G][0]         : 40    

   08 - Gain[G][1]         : 00    

   09 - Gain[B][0]         : 40    

   0A - Gain[B][1]         : 00    

   0B - Offset[R][0]       : 40    

   0C - Offset[R][1]       : 00    

   0D - Offset[G][0]       : 40    

   0E - Offset[G][1]       : 00    

   0F - Offset[B][0]       : 40    

   10 - Offset[B][1]       : 00    

   11 - SyncSeparator      : 20    

   12 - HSyncControl       : 10    

   13 - HsyncPulseWidth    : 66    

   14 - VSyncControl       : 10    

   15 - VsyncPulseWidth    : 0a    

   16 - PreCoast           : 00    

   17 - PostCoast          : 00    

   18 - ClampCoastCtrl     : f0    

   19 - ClampPlacement     : 08    

   1A - ClampDuration      : 20    

   1B - ClampAndOffset     : 5b    

   1C - TestReg0           : ff    

   1D - SogControl         : 79    

   1E - Power              : 84    

   1F - OutputSelect1      : 94    

   20 - OutputSelect2      : 05    

   21 - Reserved21         : 20    

   22 - Reserved22         : 32    

   23 - SyncFilterWindow   : 0a    

   24 - SyncDetect         : 8d    

   25 - SyncPolarityDetect : 7d    

   26 - HsyncPerVsync[0]   : 04    

   27 - HsyncPerVsync[1]   : 00    

   28 - TestReg1           : bf    

   29 - TestReg2           : 02    

   2A - TestReg3           : 00    

   2B - TestReg4           : 00    

   2C - OffsetHold         : 00    

   2D - TestReg5           : e8    

   2E - TestReg6           : 20    

   34 - SogFilter          : 00    

   36 - VcoGear            : 00    

   3C - AutoGain           : 00

To isolate the source of the problem I have done some tests :

I have connected the analog inputs 2 and 3 together to the same camera
output. The image obtained from channel 2 is OK but the one from channel 3
isn’t. So I guess that the problem is not related to my PCB on the analog side.

Still with analog inputs 2 and 3 connected together, I put the channel 2
outputs on the channel 3 PCB trace (I have adaptation resistors on each line so
it’s quite easy to do this). Both channel 2 and 3 are then OK!! So it’s not due
to the PCB traces on the digital side!!

So it remains the ADC…that’s why I’m contacting you to get some support!
I have some doubts about the ouput formatter (4:4:4 or DDR 4:2:2 etc etc)…

For your information, on the previous design we used the AD9888 and had
no problem.

  • AD9983A is quite old. Is this an existing product or a new design?


  • Hello

    you will find here some picture that could help you to  solve the problem

    bests regards


  • Hello Mattp,

    I'm the person which originally asked the question to Lionel through the french Silica Support!

    This is a new design, we have produced a first batch of prototype boards (around 20) and the full production is forecast for Q2/2013. I'm a little bit surprized, and a little bit disapointed too, because in July 2011 we've asked to Analog Devices if the AD9983A was a good solution for a new design, and the answer was "YES IT IS"! I haven't found any Analog Devices document with the mention "not recommended for new design", but your  answer lets me think that this product is now obsolete...So, is it obsolete or not? If not, is there a support on it?

    Otherwise, from a technical point of view, what is the problem? Is there a bug on the blue channel of this ADC, due to the Output Formatter mux? Due to the DDR mode?

    Don't hesitate to tell me if you've got question about my design!

    Thank you, regards, Christophe

  • Hi Christophe,

    Sorry for the confusion. I see the subject has AD9883A but the text has AD9983A.

    I assume you are asking about AD9983A. The AD9983A is okay for new designs. Our AD9983A expert is reviewing your question.


  • Hi Christophe,

    Can you provide a schematic of your board?  You can send it in a private message if necessary.


  • Hello Matt,


    Have you investigate about our problem ? Don’t hesistate to ask me any information to solve this issue!


    Best regards, Christophe


  • I talked with our AD9983A expert last week and he provided the following info:


    I don’t see any issues in their schematic right off the top of my head, so I would suggest that they try shifting the clock edge phase. They can move the clock relative to the analog data with R0x04. They have it set for 0x80, but it is valid from 0x00 in steps of 8. So, 0x00, 0x08, 0x10, 0x18, … to 0xF8. The 3 cameras are synced ( I assume) but they might not be on exactly the identical boundaries. Also, they are using one Hsync that is used for the PLL for all three cameras. There may be slight shift differences. It is possible that moving the clock phase can find a happy point for all three cameras. It is also possible that they can cause another of the channels to behave as the ‘blue’ channel is doing now.


    Please give this a try and let us know the results.


  • Hello Matt,

    I have already done this test with the ADC clock shifting, and with the value 0x00 in regsiter @0x04 I had better results on the Blue channel , but it wasn't perfect and I still had the problem (differences of 3 LSB between contiguous pixels, better than previous 5 or 6 LSB). Others channels didn't change durinf that test.

    The three cameras are synchronized, but for my test, I just use one and connect it successively on the different channels, so it's not a problem of sync signal propagation time in the cables or whatever related to a difference of delay!

    Could it be related to the output formatter of the ADC? because we have 4:4:4 or 4:4:2, SDR or DDR rate etc, which may had a slight delay on the output buffers???

    Otherwise, is the AD9888KS-170 recommended for new designs? We used this reference on the previous version of our system and it ran well...

    Regards, Christophe

  • I'm checking with the experts! I'll let you know what I find out.