Is it possible to isolate lvds signals used in FPD-Link I (1 differential clk and 5 differential data pairs) with ADN4654? Since duty cycle of clock signal is not %50, it will have DC component. Can ADN4654 handle this?
ADN4654 can be used to isolate FPD-Link I and other similar LVDS-based links like Camera Link/Channel Link.
The isolator can be used for any arbitrary data rate, right down to a DC state. So there is the capability to isolate all sequences and states, including those that are not AC-balanced.
As well, there's even a "refresh" mechanism that ensures any DC state at the output remains correct even if there are no further transitions. This is useful in any scenario that's outside the common-mode transient specification of 25 kV/us for example.
the datasheet loosely mention MIPI CS-2 application. Is there an app note available for that? I'm puzzled how can the LP and HS mode transmitted over the isolator with different levels? Do I need 2 channel each for each lane and multiplex the levels with shifters?
Have you reviewed this document at http://www.analog.com/media/en/technical-documentation/application-notes/AN-1337.pdf
We haven't handled interface and isolation part on this forum.There is separate community,Please post your questions here https://ez.analog.com/interface-isolation