Products Mentioned

ADV7181C Production
The ADV7181C is a high quality, single-chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL...
Datasheet
ADV7181C on Analog.com

  • State Verified Answer
  • Replies 6 replies
  • Subscribers 80 subscribers
  • Views 2583 views
  • Users 0 members are here
Options 

        

            Post
             Go back to editing
        

    

    


    

    









		


















	
	
			
	
			
		
	
	
		

		
ADV7181C I2C access



		

			

									
					    Eduardo
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Nov 20, 2012 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    We are at the early stages of debugging a video board using the ADV7181C video serialiser.
    
 
    When I write (R/W = W) a command through the I2C interface to the chip using address 0x21 (or 0x42 as stated in the manual) I receive an ack per each byte sent. This is good 
    
 
    But  when I try to receive data (R/W = R) from this same address the address byte is not acknowledged and of course no communication takes place.
    
 
    The manual creates some confusion in my mind about the I2C address, should it be shifted, should it not! Although I've tried all possible addresses and the only that is acknowledged when writing is in fact 0x21.
    
 
    Could anyone give me some ideas about this? 
    
 
    thanks
    
 
      Eduardo
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 Video Products
                
                                                    
                 adv7181c
                
                                                    
                 Video Decoders
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



Parents
	
      
	

    • 
	
      



	
		
	
	



      
	
      
		
      
							FormerMember
					
      
		
      
			
													0
							
			
				
									FormerMember
							        
			
			
			
    
            
						
                            
            
            				
            
                on Nov 20, 2012 5:15 PM
            
            
					
    
	
    

		
		
    
					
    In Read Mode, the highest subaddress register contents continue to be output until the
    
 
    master device issues a no-acknowledge. This indicates the end of a read. A no-acknowledge
    
 
    condition is where the SDA line is not pulled low on the ninth pulse.
    
 
    I think this is what you are referring to.  A master NACK during the read back byte stops the read back.  In absolute I2C standards probably not but for this part it's ok since you can only access one register at a time and the subaddress register does not auto-increment so doing another byte read will just return the same byte you just read.  A stop essentially kills the transaction anyways.  This is an older device
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    


	



Reply

      


    • 
	
      



	
		
	
	



      
	
      
		
      
							FormerMember
					
      
		
      
			
													0
							
			
				
									FormerMember
							        
			
			
			
    
            
						
                            
            
            				
            
                on Nov 20, 2012 5:15 PM
            
            
					
    
	
    

		
		
    
					
    In Read Mode, the highest subaddress register contents continue to be output until the
    
 
    master device issues a no-acknowledge. This indicates the end of a read. A no-acknowledge
    
 
    condition is where the SDA line is not pulled low on the ninth pulse.
    
 
    I think this is what you are referring to.  A master NACK during the read back byte stops the read back.  In absolute I2C standards probably not but for this part it's ok since you can only access one register at a time and the subaddress register does not auto-increment so doing another byte read will just return the same byte you just read.  A stop essentially kills the transaction anyways.  This is an older device
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    





Children
	
    No Data