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ADV7181C Production
The ADV7181C is a high quality, single-chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL...
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ADV7181C on Analog.com

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ADV7181C I2C access



		

			

									
					    Eduardo
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Nov 20, 2012 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    We are at the early stages of debugging a video board using the ADV7181C video serialiser.
    
 
    When I write (R/W = W) a command through the I2C interface to the chip using address 0x21 (or 0x42 as stated in the manual) I receive an ack per each byte sent. This is good 
    
 
    But  when I try to receive data (R/W = R) from this same address the address byte is not acknowledged and of course no communication takes place.
    
 
    The manual creates some confusion in my mind about the I2C address, should it be shifted, should it not! Although I've tried all possible addresses and the only that is acknowledged when writing is in fact 0x21.
    
 
    Could anyone give me some ideas about this? 
    
 
    thanks
    
 
      Eduardo
    
									
			        
		
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	
    
		
	
    















    
	
    
	
    
					



			


				
	









	
      
	

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													0
							
			
				
									
							        
			
			
			
        
            
			                            
                        
                on Nov 20, 2012 12:07 PM
            
            
					
        
	
        

		
		
        
					
        I was able to find some clue about the abnormal behaviour related before.
        
 
        According to the ADV7181C_Manual_RevC.pdf a read sequence should be as follows (see also the picture attached):
        
 
        START  SlaveAddr  Ack(Slave)  SubAddr  Ack(Slave)  START  SlaveAddr  Ack(Slave)  Data  Ack(Master)  ...  Data  /Ack(Master)  STOP
        
 
        Apparently the ADV7181C expects two START bits in order for a read sequence to be done.
        
 
        Can some one acknowledge that this is the proper way to do a read?
        
 
        thanks
        
			
        

		
			
	      

				
        
			
			
		
        
			
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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							FormerMember
					
        
		
        
			
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									FormerMember
							        
			
			
			
      
            
			                            
                        
                on Nov 20, 2012 2:15 PM
            
            
					
      
	
      

		
		
      
					
      Reading back is a 2 step process. First you write the index register address you want to read back from and then send another Start bit, slave read address and then read back the data.  The second Start is sometimes referred to as a repeat start.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      


	

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													0
							
			
				
									
							        
			
			
			
        
            
			                            
                        
                on Nov 20, 2012 5:01 PM
            
            
					
        
	
        

		
		
        
					
        thanks for your answer.
        
 
        It is working now 
        
 
        Allow me another question.
        
 
        In the same context the frame to be sent is:
        
 
        START  SlaveAddr  Ack(Slave)  SubAddr  Ack(Slave)  START  SlaveAddr  Ack(Slave)  Data  Ack(Master)  ...  Data  /Ack(Master)  STOP
        
 
        For some reason the manual indicates that the last byte of Data should be NOT Acknowledged by the Master.
        
 
        Is this the proper action? (I thought that the transfer of data from the slave would be terminated when the master used the STOP.) 
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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							FormerMember
					
        
		
        
			
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									FormerMember
							        
			
			
			
            
			                            
                        
                on Nov 20, 2012 5:15 PM
            
            
					
        
	
        

		
		
        
					
        In Read Mode, the highest subaddress register contents continue to be output until the
        
 
        master device issues a no-acknowledge. This indicates the end of a read. A no-acknowledge
        
 
        condition is where the SDA line is not pulled low on the ninth pulse.
        
 
        I think this is what you are referring to.  A master NACK during the read back byte stops the read back.  In absolute I2C standards probably not but for this part it's ok since you can only access one register at a time and the subaddress register does not auto-increment so doing another byte read will just return the same byte you just read.  A stop essentially kills the transaction anyways.  This is an older device
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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													0
							
			
				
									
							        
			
			
			
          
            
			                            
                        
                on Nov 21, 2012 5:13 PM
            
            
					
          
	
          

		
		
          
					
          Is there any application Note for the ADV7181C?
          
 
          I'm finding difficult  to find out which registers to program...
          
 
          thanks
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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							FormerMember
					
          
		
          
			
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									FormerMember
							        
			
			
			
            
			                            
                        
                on Nov 21, 2012 5:27 PM
            
            
					
          
	
          

		
		
          
					
          The design support files can be found at
          
 
          http://ez.analog.com/docs/DOC-1621
          
 
          It contains a set of scripts to configure the device for operation.
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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