AD8195 and DDC buffers

Hi,

     we have implemented the same circuit proposed by the eval schematics and AD8195 datasheet. The DDC lines on HDMI connector side are 47KOhms 5V PU and 2KOhms 3.3V PU on FPGA side. Our schematic look like this one:

At the probe point highlighted in Magenta we observe the following glitch produce by AD8195:

Obviously this glitch fails the DDC communication and we would like AnalogDevice to help us understanding and fixing this issue.

Thanks,

Steph.

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