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some problems about AD9824

After configerating register through SPI .The problem comes out, the input is a 1.5V DC voltage,But the output is not zero.This problem has bothered me for a long time.In thoery, the output is zero when the input is DC voltage. So i hope someone can help me to solve this problem.

  • Yes, in theory the CDS output would be zero with a DC input voltage. However, there are offset voltages in the CDS/VGA/ADC circuits which can cause the output level to be higher than zero scale with a DC input voltage. Also, if there is a non-zero value in the CLAMPLEVEL register, this will also add additional offset to the output level.

  • The output do not change when I change the CLAMP level register. I tried not to configure the register. I only use the sampling clock and dataclk,but the output is the same as before.It has output within the scope D0~D10. Then I want to ask how can I check the offset voltages in the CDS/VGA/ADC circuits. Thank you very much.

  • What is the status of the CLPOB and CLPDM signals? The CDS circuit cannot bias properly without using the CLPDM input signal. If you only use a DC input voltage connected to CCDIN, then it is possible to set CLPOB and CLPDM to be "active" continuously by setting these pins LOW (while using default values). This configuration should produce a digital output value equal to the CLAMP LEVEL register value, because the clamping is always turned on.

  • Now,I only make three signals (SHP,SHD,DATACLK) effectively, and I even do not use the SPI port. The output is still not zero, and It has output within the scope D0~D10. I hope you can help me. Thank you!

  • Can you please confirm the status of the CLPDM and CLPOB signals- this chip is not intended to operate without providing these signals.

  • Sorry, I do not describe the problem clealy tomorrow. The status of the CLPDM and  CLPOB  is 1. I only make three signals (SHP,SHD,DATACLK) effectively, and I even do not use the SPI port. And the input is also a DC voltage.

  • With CLPDM and CLPOB disabled, there will be two problems- the CDS will not be able to properly bias, and the offset correction loop (controlled by CLPOB) will not be able to correct the offset from the analog signal path. I recommend that you create a clamp pulse for CLPOB/CLPDM, such as the one shown in Figure 6 of the data sheet.

  • AD9824 the exposed pad need to connect to ground? i found when i configure register ,i read the register is error,please tell me why?

  • We recommend that you connect the exposed paddle to GND.

    Regarding the register write/read operation, please confirm your serial timing waveforms to make sure they matches the data sheet specifications. You should be able to write a specific value to any register and successfully read back the same value, but there could be an issue with set-up/hold times, or glitches/ringing on the serial interface signals.

  • hi:

              i have a question to ask you,when i write the register single,i read the register ,the write date and the read date is ok  ,but when i configure the operation register ,Control register ,VGA register ,PXGA register ,i found  i read the date is not equal to the wirte date,i can not understand,thanks for your help.

             now ,the ccd works well,i want to konw why the read and write date is not equal.thanks for your help.

             i use the AD9816 ,AD9824,the read and write date is equal.

             fiuure 1: write and read register

             figure 2 :continous configer the register