There are so many modes of audio port AD7611 can output,I'm using the I2S TDM mode now(audio data output from pin ap only),It can output 7.1 and up to 48k(24bit) per channel by reading the datasheet.
It confuses me a lot,the audio mode is decided by the source,If the source outputs higher than 48k(24bit) per channel,for example it's 192k or 88.2k,How AD7611 deal with it?It will delect some words and output 48K per channel?
Can AD7611 output 7.1 and higher than 48k(24bit)?if it dose,how I must do with my PCB?
32k,44.1k,48k,88.2k,96k,176.4k,192k are all good for ad9889b,Those modes need different frequency of audio clocks,I use plls in FPGA to regenerate the audio clocks,But I find that FPGA can't generate exact freqency of audio clock,for example:AD9889b needs 12.288MHz for 192k,But FPGA only give 12.289MHz,Can AD9889B work?
I've read ADF4002 and ADF4360-9,ADF4002 is more complicated in my oppinion,I have to build the external loop filter and VCO if I use ADF4002,but it's a very truble thing to pick up these parameters.So I decide to use ADF4360-9 to test first.
There are many tested results to be signed out with frigures in the datasheet of ADF4360-9,the freqencies of PFD are all about 1MHz and the jitter of output clock is exceptable.How about the jitter is when the frequency of PFD runs at about 60KHz?Did you tested that situation before?
I do know higher frequency of PFD can cause higher performance to reduce jitter on output,The situation of my project was talked to you earlier,can the serdes be drove by the output clock of ADF4360-9 and work normally?
I know the situation is very special and cause fewer options,if ADF4360-9 can't do this,can anyothers do?