hi,
when adv7481 bringup in our board, then we used SONY DV HDR-CX405 as input.
if the DV is set 720P, then the data after adv7481 is okay. but if the DV is set to 1080P, then the data after adv7481 is broken as attached, and it could keep long time with such kind broken data.
so that is the same DV, but differnet set leads to differnt result. I checked the datasheet, it seems to support 1080P with HDMI interface. and the kernel log shows adv7481 can detect the right size from HDMI.
adv7481_get_hdmi_timings(2035), adv7481 TMDS Resolution: 1920 x 1080 @ 60 fps
could you help to check and share some clue? Thanks so much.
Hi, In your configuration,output video seems like 4:2:0 format. But we don't see any 4:2:0 conversion in ADV7481 part.Please refer ez.analog.com/.../adv7481-design-support-files
Note: The video data output by the HDMI/MHL section is always in a 4:4:4 format with 36 bits per pixel.This is irrespective of the encoding format of the video data encapsulated in the HDMI/MHL/DVI stream input to the HDMI/MHL Rx section (that is, 4:2:2 or 4:4:4).
Thanks,
Poornima
hi Poornima,
Thanks for your reply. the screenshot is the HDMI section + ISP process. so that you saw it's 4:2:0.
actually we configured as the guide said, and tested with this SONY DV, 720P is okay, and the the preview on screen is good. but 1080P is broken as above.
I am not sure if there is some config or setting could adjust to make it work well, could you share some guide or clue?
thanks a lot.
There is no other source(DV/JVC) could support 1080P HDMI in, so I cannot test it.
we configured VID_STD register with 0x4A, it's 720x480p60 by default.
I checked the Hardware manual, it looks like ADV7481 cannot support 1080P@60fps.
if the input is 1080P@60fps, is there any possible that ADV7481 receive or handle interval frame to make the input as 1080P@30fps? such as handle 1 frame, then drop 1 frame, then handle 1 frame, drop 1 frame, ....
Hi,
But CSI-TXA 4-Lane Output Mode can support 1080p@60fps, Refer Page209 in ADV748x Hardware manual.
Both the 1-lane MIPI CSI-2 Tx and the 4-lane MIPI CSI-2 Tx are disabled by default. To enable either of the MIPI CSI-2 Txs, the appropriate control must be enabled, either csi1_en or csi4_en.
Thanks for your suggestion, but the board design is done very early, so only 2 lanes could be configuered, is there any way to make it work with 2 lanes by reducing the ADV7481 process received data, such as receive or handle interval frame to make the input as 1080P@30fps? for example, handle 1 frame, then drop 1 frame, then handle 1 frame, drop 1 frame, ....
This progressive format is not possible in 2-lane. But we can support for interlaced one.
okay, thanks very much for your verification.