Hi all,
first of all, thanks for the help you will give us.
Scenario:
- ADV7393 PAL encoder is attached to the output of the LVDS controller of my board. The LVDS output is RGB 16(565) with resolution of 640x480. I would like to generate the output of ADV7393 as PAL signal with SD definition in square pixel mode.
The input clock of ADV7393 is 29.5MHz. My setup of registers is the one reported in table 97 of the datasheet :
Subaddress Setting Description
0x17 0x02 Software Reset
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x11 PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled.
0x82 0xD3 Pixel data valid. CVBS/Y-C (S-Video) out. SSAF PrPb filter enabled. Active video edge control enabled. Square pixel mode enabled.
0x87 0x80 RGB input enabled.
0x88 0x10 16-bit RGB input enabled.
0x8A 0x0C Timing Mode 2 (slave). HSYNC/VSYNC synchronization.
Subcarrier frequency register values for CVBS and/or S-Video (Y-C) output in PAL square pixel mode (29.5 MHz input clock).
0x8C 0x0C
0x8D 0x8C
0x8E 0x79
0x8F 0x26
But nothing is snown on my display (PAL) attached to DAC1 of the ADV7393.
- Question:
- do the LVDS output signal (input of the ADV7393 encoder) have some "constraint" in timing (e.g. HSYNC, VSYNC timing) that will allow the ADV7393 to generate the PAL output ?
- are my setting correct or I miss something ?
Best Regards,
A.Biasci.