[PAL] ADV7393

Hi,

Have you checked the scripts from Design support files https://ez.analog.com/video/w/documents/801/adv739x-design-support-files

Please, also try to enable the internal test pattern - register 0x84 bit 6 and check whether the same behavior or not.

Thanks,

Poornima

Hi Poornima

           we tried to look at your link but we didn't find anything can help us.


I will try to explain more in details our configuration:
    - we would like to have as output of ADV7393 a PAL (square pixel) signal in CVBS.
    - input data are attached to an LCD controller in 16bit RGB(565).

We applied table 93 of ADV7393 user-manual (ADV7390/ADV7391/ADV7392/ADV7393 revJ)
as ADV7393 settings but it didn't show anything on the attached screen to DAC1
of ADV7393.

We are not sure about the format of the input signal to provide to ADV7393
in order to have the PAL output. The CLKIN of ADV7393 is at 29.5MHz and the pixel clock is the same. We are
able to drive the HSYNC/VSYNC signal of the LCD controller.


Question:
    - what are the inputs timing and resolution that the LCD controller should
    provide to the ADV7393 in order to see a PAL signal on output ?
        (e.g. HSYNC/VSYNC timing, valid resolution of LCD controller to provide
         to ADV7393, ...).

    - the sentence in datasheet:

            In 16-Bit 4:4:4 RGB Mode, the pixel data is updated at half the rate of the clock, that is, at a rate of 13.5 MHz (see Figure 6)

       is valid also for SD square pixel mode ?

Best Regards,
        A.Biasci.

Hi,

16-Bit 4:4:4 RGB mode is Only external syncs can be used though in this mode, not embedded syncs.
The clock would obviously be half normal at 13.5Mhz as well.
Note: Embedded EAV/SAV timing codes are not supported with SD RGB mode.Also, master timing mode is not supported for SD RGB input mode, therefore,external synchronization must be used.

Square Pixel Mode can be enabled by register 0x82[4]. Note that for CVBS and S-Video  (Y-C) outputs,
the SD subcarrier frequency registers must be updated to reflect  the input clock frequency used in SD square pixel mode.Also note that the SD  input standard auto detection feature must be disabled in SD square pixel mode  (this is disabled by default after reset)
Apply the clock and enable internal color bars. If you have programmed correctly you should get proper color bars and color sub carrier output.After that configure the input to math the format you are applying.

Thanks,

Poornima

Hi Poornima,

                          thanks for your reply. We are modifying our prototype to achive the half-rate pixel clock.

Some more question:

• are there any constraint on HSYNC/VSYNC timing in SD square pixel mode?
  • e.g. HSYNC should be Xns
  • e.g. VSYNC shoul be Yms
• can I provide, as input, an RGB 4:4:4 with 640x480 as active resolution, coming directly from LCD controller or the input signal must have the resolution of SD square pixel standard?

Thanks again for your help.

Best Regards,

                A.Biasci.

Hi,

For NTSC operation, an input clock of 24.5454 MHz is required. The active resolution is 640 × 480.

For PAL operation, an input clock of 29.5 MHz is required. The active resolution is 768×576.

The output from this part seems to be programmable, which should enable you to output the exact timing expected at the encoder.And also ADV7393 can only provide external syncs based on EAV/SAV time codes that it receives. It can't generate timing

Thanks,

Poornima

Hi Poornima,

                   thanks again for your help. Let me summarize for PAL square pixel:

• 29.5MHz is the clock to provide to ADV7393
• 14.75MHz is the pixel rate to provide to ADV7393
• 16 bit RGB 4:4:4 is the output of my LCD controller (input of ADV7393)
• the resolution to provide as input to ADV7393 (output of my LCD controller) is 768×576
• frame rate is 25 fps
• HSYNC/VSYNC timings are reported in the table above

So ADV7393 does not performs any scaling/adjusting of the input signal. It "only" performs a sampling of digital data to provide, as output, a signal compliant with PAL square pixel (supposing I configured the chip correctly).

Are this summary correct? I will provide to you a feedback once we have the solution in place.

Best Regards,

             A.Biasci.

Hi Poornima,

                   thanks again for your help. Let me summarize for PAL square pixel:

• 29.5MHz is the clock to provide to ADV7393
• 14.75MHz is the pixel rate to provide to ADV7393
• 16 bit RGB 4:4:4 is the output of my LCD controller (input of ADV7393)
• the resolution to provide as input to ADV7393 (output of my LCD controller) is 768×576
• frame rate is 25 fps
• HSYNC/VSYNC timings are reported in the table above

So ADV7393 does not performs any scaling/adjusting of the input signal. It "only" performs a sampling of digital data to provide, as output, a signal compliant with PAL square pixel (supposing I configured the chip correctly).

Are this summary correct? I will provide to you a feedback once we have the solution in place.

Best Regards,

             A.Biasci.

Hi,

 Yes,ADV7393 cannot do any scaling,It can only support the formats indicated in Table 1 of the datasheet.

Thanks,

Poornima

Hi Poornima,

                    thanks for your help. Unfortunately, we still have problem to configure the chip. Question:

• the input provided to ADV7393 to produce an output compliant to PAL-square pixel mode, must be interlacced?

Best Regards,

                    A.Biasci.

Hi,

 Yes, ADV7390/ADV7391/ADV7392/ADV7393 support an SD non-interlaced mode. All input configurations, output configurations,and features available in NTSC and PAL modes are available in SD non-interlaced mode.

Thanks,

Poornima

Dear Poormina,

                     I couldn't find this kind of configuration in the ADV7393 datasheet Rev J. Could you help me?

The Table 63 on page 92 of the datasheet, for SD-mode, always reports as Input Format an interlaced mode but not progressive.

Progressive Input Format(s) are reported only in Table 98 on page 99 for Enhanced Definition.

Regards,

      A.Biasci.

Hi,

 Please refer Page52 in datasheet for more details about SD non-interlaced mode.

Thanks,

Poornima

Dear Poornima,

              thanks again for your help. Could you confirm our setup in order to generate a PAL square-pixel output:

• CLKIN is 29.5MHz
• Pixel Clock is 14.75 MHz
• Input Format is 16 RGB565 --> 756x288p
• Output of ADV7393 is CVBS

We are trying to calculate the timings of LCD controller to generate the correct signal at 756x288p to provide as input to ADV7393.

Questions:

• there are a reference timing that HSYNC/VSYNC signals must have?
• there is a constraint about the time between HSYNC and the first valid pixel of the frame?
• there is a constraint about the time between VSYNC and the start of the new frame?

Datasheet does not report any timing about our configuration (SD noninterlaced mode), so any help will be very appretiated.

Best Regards,

A.Biasci.

Hi,

 I beleive,ADV7393 does support 288p digital in and will output this as 288P analogue video. It cannot convert 288P (SD non-interlaced) to PAL interlaced output.

The timing we are expecting is described in CEA861B formats 8 & 9. We do not publish output video timing formats in datasheets.

Thanks,

Poornima