Schematic verification


I am working on a board for video application.

I am getting an analog csync which can have voltage level of 0.0V to 2.2V coming from another system. But as per stanag3350B standard the voltage for the csync can be -30% of the video signal. Timing of the csync will be as per STANAG3350B standard which should be maintained at the output as well I am feeding this CSYNC signal [EXT_CSYNC_IN +/-] to AD8145 to convert the differential signal to single ended signal.

The signal is then fed to AD818 to generate 13 CSYNC signals using the o/p of AD8145. The outputs generated by AD818 is then fed to AD8146 which converts the single ended signals to differential signals. The distance for the CSYNC would be 13 meter max. These CSYNC signals will be connected to different systems and each system will have a load of 120 ohm. So kindly verify the connectivity using the attachment.






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