Post Go back to editing

AD9388A equalization registers

Hello there,

The hardware user guide and the recommended register settings both recommend these values for TMDS eq registers above 160MHz:

For TMDS frequencies of 160 MHz or greater:

•  User Map 2, set register 0xF0 to 0x30

•  User Map 2, set register 0xF1 to 0x0F

•  User Map 2, set register 0xF4 to 0xA0

However the reference source code implements these values in a different way:

if(w_tmds_freq < 0xA0) {


} else if(w_tmds_freq > 0xA0) {

                    ATV_print("Equaliser setting >160");

                    ATV_i2c_1_wr_8_8(VRX_USER_2_MAP_ADDR, 0xF0, 0x10);

                    ATV_i2c_1_wr_8_8(VRX_USER_2_MAP_ADDR, 0xF1, 0x0F);

                    ATV_i2c_1_wr_8_8(VRX_USER_2_MAP_ADDR, 0xF4, 0xA0);

                    return 2;


As you see, the value of the F0 register doesn't match. I would like ask which one is better.

The reason why I'm asking this, because we have performance issues at significant amount of the chips. Our factory department tests the new devices with a good quality 30m 22AWG cable, 1600x1200@60 (165Mhz) resolution. The majority of chips passes the test while others not. By playing the above registers it seems possible to get a stable picture in every case, however values for best performance are differs from device to device.

Thats why I would like ask what are these registers exactly do. At least it would be great to know, what are the valid ranges, are they scalar values and where are the MSB/LSB bit positions.

Thank you for your help in advance

Parents Reply Children
No Data