Post Go back to editing

ADV7125 & AD724

We want to implement a system with PAL video output or VGA monitor.

1. For a PAL solution we want to use the ADV7125 for digital to analog conversion and the AD724 for analog to composite video. We saw in the datasheet of the AD724 (page 11) that it may be possible to use this solution because there is an example circuit using the ADV7120 (similar part to the ADV7125).

Our question is about the voltage level of the green output of the ADV7125.

In the datasheet of the ADV7125 you can see that  BLANK level of the green output is around 0.2V and WHITE level is around 0.9V (page 11). The AD724 only supports the standard 0V for BLANK and 0.7V for WHITE. Can we use ADV7125 in conjunction with the AD724 although the level is not correct? What will the consequences be? Are there any workarounds?

We don’t understand how it is possible to use the ADV7120, for example, with this level of voltage.

2. For the same reason for VGA, can we use ADV7125 to generate the green color although the level is not the standard also?

What will the consequences be?

If you compare ADV7120 Figure 3 with ADV7125 Figure 5 you will see that the output wave forms are almost identical.  The series AC blocking caps to the AD724 will level shift the voltage to the right levels for the AD724 to work.

Analog video is treated as an AC signal with blank to white level = 0.7 Volts.  The DC offset is corrected with the blocking caps.  Normally video is defined as 1Vpp when you include the sync pulses.  The peak to peak pulse levels are as shown in ADV7125 Figure 5.

  • Hi Chris,

    Just remember that the RGB that's fed into the AD724 must be interlaced.

    --Jonathan

  • Hello,

    First at all thanks for the answer. It will be very useful for us.

    We have a second part of the question about to use the same part ADV7125 to generate a standard VGA output.

    How can we correct the level of the green ? Adding serial caps also ?

    Thanks.

  • If the analog green input is greater then that spec'd by the part then you can change the input 75 Ohm resistor into a divider network to lower its peak to peak value.  As an example, we do this for the ADV7842 inputs.  Check out UG-214 Figure 171 where we have a 24 Ohm series resistor and a 51 Ohm to ground to reduce the peak to peak voltage while maintaining the 75 Ohm load requirement.

    https://ez.analog.com/docs/DOC-1712


  • Hello,

    Thanks for the answer. But our case is not the input. We design video cards using FPGA technology. Now we are evaluating to make 2 different outputs for different applications.

    For the first case, composite PAL video, the solution is ADV7125 & AD724 (INTERLACED). All it's ok and many thanks for the support.

    For the second case is a standard VGA compatible (D sub 9) resolution of 640x480x60 Hz. For this case we want to use also the ADV7125 to generate the analog color video signal. The problem is that this part in blank level give 0V in the red and blue but 0.271 V in green. In white level give 0.7V in red and blue and 0.975 V in green. All of that with pin 12 of ADV7125 (high=no sync)

    The green levels are above of the VGA standards levels. How can we solve this ? Is it ADV7125 a suitable DAC to use it for PC VGA video standards ?

    Are the levels explain it here corrects ? Is this the behavior of this part ?

    Thank you very much.

    Regards.

  • The ADV7125 should work fine to drive a DB-9 connector.

    1) /SYNC should be tied to logic 0 if there is to be no sync pulse on the green line., turns off 40IRE current source.

    2) Rset can be tweaked to effect the output voltage dependent on the load impedances.  The 3 channels should track..

    3) Figure 10 shows the typical configuration for the VGA driver.

  • Thank you for the answer.

    Now it is clear that we need to tied to ground  /SYNC to turn off 40IRE.

    It's very strange because the signal is negate and also if you see this post above in the figure 16 of the AD724 the ADV7120 (very similar part and equal functionality of ADV7125) this pin is tied to VCC, so the sync signal is turn on.

    Is it a mistake in the drawing of the figure 16 ?. There's no sense to generate this signal because the input level of the AD724 only goes to 0.7V. You don't need this signal for PAL video because you have HSYNC AND VSYNC.

    Why is tied high ?

    Thanks. Regards.

  • Not sure, it confused me at first too.  This is an old part so there might be issues that never got corrected in the data sheet. I just don't know the history of this part.

    This part can also drive component with SOY with the sync pulses on the Y channel so the /SYNC needs to be there for that.  This part wasn't designs to drive NTSC or PAL unless you are only doing monochrome, (RS343/RS170).

  • Hi Chris,

    We finally implemented the design for ADV7125 & AD724 for our clients.

    We used the ADV7125 for two different applications. The first one is for VGA analog video DAC generator. It's works really fine !!

    The other use is to generate the analog R,G,B signals to input to a AD724 composite video codec. We have followed all the recommendations in the design and PCB, but we didn't have a good result. Syncs signals are pretty good and the image (full red screen for example) is stable, doesn't move in the screen, but color is no good.

    We have tested with different colors (full red, full blue, full green) and the result is a grey screen , a little brightness gray screen, and strange behavior as you see in the pics.

    We used the part (AD724) as follow:

    1) Only one field is generated, so we have 312 lines for PAL, and always is the same field. We didn't generate the equalizing pulses. So for interlace video we have the same picture at 50Hz. This technique are wide extended and we have use it in the past with other codecs without problems. We think that this is not the problem because the image is stable in the screen.

    2) We used a standard television, CRT, LCD.

    3) For clock to the AD724 we have used a part to program NTSC clock or PAL with good accuracy. This clock is not synchronized with synchronization signals, is a clock independent. The result is the same as you used an external crystal independent of the synchronization signals.

    Could you help us ? Any idea of what is happens ? Is the part used for the sub-carrier clock good enough ? Is this the problem ?

    When you have this result in the color what could be the cause ? We have designed other composite video with other parts and didn't have this effect. What is wrong in our design ?

    We have attached the schematics for the system and some screen shots (the image is full screen but you only see one part brightness for the refresh of the camera used to take the picture).

    Thank you very much.

    Regards.