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ADV7391 and HSYNC

I am starting a new project and wish to use the external control signals rather than the embedded code in the data stream. My question is related to the timing of the HSYNC input signal to the device. It is not clear from the data sheet as to the timing of the HSYNC relative to the data stream. I am making the assumption that it should occur during the non-active video data period in the data stream and I am also assuming that it should be asserted throughout the same period. Comments please?

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  • FormerMember
    0 FormerMember
on May 23, 2013 7:27 PM

Composite video timing is based on the SMPTE-170 standard (analog),  There are lots of web sites that describe this timing.  You can also check out of ADV7172 data sheet, it has some good timing diagrams

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  • FormerMember
    0 FormerMember
on May 23, 2013 7:27 PM

Composite video timing is based on the SMPTE-170 standard (analog),  There are lots of web sites that describe this timing.  You can also check out of ADV7172 data sheet, it has some good timing diagrams

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