The color burst from AD723 seems to move on AD723 Eval Board.

Hello,

Thank you for your reply.

There are monitors that generate chroma not by referring input color burst but by referring color burst generated by itself from HSYNC.
When output from AD723 (has the moving burst) connects to the monitor, it seems that we can see abnormal chroma on the monitor.

According to your comment,
I think asynchronous 4FSC causes moving the start point of color burst.
Is it right?

How much phase does the start point of color burst move at the maximum?
Is it one subcarrier (3.579545MHz for NTSC)?

Thank you!

Best regards.
Tamu

I'm trying to get more information form the AD723 expert on this issus.

Hello Tamu,

Yes, you are correct.  The phase varies because the two signals are not synchronous, so cycle-slipping occurs between them.  The NTSC specification requires a fixed 19-cycle phase relationship between the 50% point of the Hsync leading edge and the first rising edge of the colorburst signal, but some systems can operate asynchronously.  If you are using the eval board with the autonomous clock oscillator, you are operating asynchrnously.  Do you have a reference clock available that is synchronous with your sync pulses?  You will need this for synchronous operation.

Best regards.

--Jonathan

Hello Jonathan,

Thank you for your reply.

I thought I'd like to try synchronous operation.
But unfortunatly, I can not try it  because of our SG and system.

About my first question, I understood the asynchronous 4FSC causes moving the start point of color burst.

Please let me confirm about my second question.
>How much phase does the start point of color burst move at the maximum?
>Is it one subcarrier (3.579545MHz for NTSC)?

Is one subcarrier (3.579545MHz for NTSC) right?
or is it one 4FSC (14.318 180 MHz for NTSC)?

Thank you!

Best regards.
Tamu

Hi Tamu,

The colorburst gating signal is generated after counting 4FSC cycles following the falling edge of the Hsync pulse, so the greatest phase error would be one cycle of 4FSC, or 90 degrees at 3.579545 MHz.

Best regards.

--Jonathan

Hello Jonathan,

Thank you very much for your reply.

This is last question for this issue.

>so the greatest phase error would be one cycle of 4FSC, or 90 degrees at 3.579545 MHz.

I think this is the greatest phase error Even if it is a case where temperature and process change.

Is this right?

Thank you!

Best regards.

Tamu

Hi Tamu,

You can't get completely away from variations due to temperature and process, but I would expect the deltas due to these to be small compared with the maximum phase ambiguity due to the two signals being asynchronous.

Best regards.

--Jonathan

Hi Jonathan,

Thank you for your reply.

I'm so sorry for many questions.

Question 1.

About your following comment,

>The colorburst gating signal is generated after counting 4FSC cycles following the falling edge of the Hsync pulse,

I'd like to know the schematic for color burst insertion.

Please refer attached file "Color_burst_insertion_logic.pptx".

Question 2.

Let me confirm about your following comment.

>the greatest phase error would be one cycle of 4FSC, or 90 degrees at 3.579545 MHz.

We'd like to know the accuracy of the phase error.

May we consider only variations of external OSC generating 14.318180 MHz?

Is there possibility that the phase error is more than one 4FSC depends on variations of the color burst insert logic in AD723?

Thank you!

Best regards.

Tamu

Hi Tamu,

I don't have the schematic that shows exactly how the colorburst is gated.  The block diagram you attached is very high-level and essentially shows pictorially what is described by the phrase in my earlier reply that you quoted, so I'm not sure what you are asking.  The same description is given in the data sheet.

The fact remains that the Hsync and 4FSC signals are asynchronous.  The counter that is clocked by 4FSC is enabled when the falling edge of the Hsync pulse reaches its nominal midpoint, but the phase of the 4FSC clock is indeterminate at that point in time because it is not synchronous with the Hsync signal.  The 4FSC phase could, therefore, be anything between 0 and 2pi when the counter is enabled.  This is where the ambiguity comes from, which amounts to 90 degrees at the colorburst frequency.  The phase of the colorburst will change by the same amount each time it is inserted because the Hsync signal and 4FSC signal are cycle-slipping relative to each other at a constant rate.  (If you put the two asynchronous signals on a scope and triggered on one, the other would be seen to slip past the one that the scope is triggered on.)  This is the main source of the phase ambiguity.  Propagation delays will introduce a fixed time shift, but the variations, or deltas, will be due to the cycle-slipping.  Any variations with temperature will be small enough to ignore.

Best regards.

--Jonathan