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ADV7612 16BIT SDR

i want the adv7612 output 16bit YCbCr with vsync ,hsync and de.

I sellect 16BIT SDR ITU-BT-656 Mode 0 with set the value  98,03, 80

the regs value setting :

98 ,00, 02,

98,01, 06,

98,02, F5,
98, 03, 80,
98, 04, 62,
98, 05, 29,
98, 06, A6,
98, 0B, 44,
98, 0C, 42,
98,14, 7F,
98,15, 80,
98,19, 83,
98,33, 40,

44,BA, 01,

64,40,81

68 9B 03 ; ADI recommended setting

68 00 08 ; Set HDMI Input Port A (BG_MEAS_PORT_SEL = 001b)

68 02 03 ; Enable Ports A & B in background mode

68 83 FC ; Enable clock terminators for port A & B

68 6F 0C ; ADI recommended setting

68 85 1F ; ADI recommended setting

68 87 70 ; ADI recommended setting

68 8D 04 ; LFG Port A

68 8E 1E ; HFG Port A

68 1A 8A ; unmute audio

68 57 DA ; ADI recommended setting

68 58 01 ; ADI recommended setting

68 75 10 ; DDC drive strength

68 90 04 ; LFG Port B

68 91 1E ; HFG Port B

when i change the Resolution to 1920*1080, there display,but a litter time ,it disapper,

is there any problem with regs setting .

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  • FormerMember
    0 FormerMember
on May 30, 2013 2:44 PM

One possible cause of this problem is the phase relationship between the output pixel clock and the pixel data.  LLC_DLL_PHASE=0x83 was set for our evaluation board.  It is board dependent.  I suggest testing each of the 16 possible PHASE adjustments to find one that works.  This only has to be done once and then this new phase adjustment should work for all other boards of the same design.  This problem is most prevalent at the highest resolutions such as 1080p where the clock rate is highest.  By the way, this type of test data is called a "Schmoo plot".

You may be able to measure the correct frequencies on VCLK and the sync lines but sink may  be having problems latching on to them correctly.  Again try each phase setting to verify.

Have you tried a DVI source to make sure this is not HDCP related?

Another possible cause is the input layout is not correct causing problems at the higher frequencies.

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  • FormerMember
    0 FormerMember
on May 30, 2013 2:44 PM

One possible cause of this problem is the phase relationship between the output pixel clock and the pixel data.  LLC_DLL_PHASE=0x83 was set for our evaluation board.  It is board dependent.  I suggest testing each of the 16 possible PHASE adjustments to find one that works.  This only has to be done once and then this new phase adjustment should work for all other boards of the same design.  This problem is most prevalent at the highest resolutions such as 1080p where the clock rate is highest.  By the way, this type of test data is called a "Schmoo plot".

You may be able to measure the correct frequencies on VCLK and the sync lines but sink may  be having problems latching on to them correctly.  Again try each phase setting to verify.

Have you tried a DVI source to make sure this is not HDCP related?

Another possible cause is the input layout is not correct causing problems at the higher frequencies.

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