Dear ADI expert,
Customer has saw video jitter at output of ADV728XA-M when using I2P function.
And I also saw other post mentioning : https://analogdevices.telligenthosting.net/video/f/q-a/7704/adv7280-cvbs-ntsc-i2p-how-suppress-the-image-jitter
But since It's ADV7280 which is older part, so whether is this jitter artefact also expected for ADV7280A version? (any design change to improve this issue?)
Thank you very much!
If you are using the interlaced to progressive (I2P) block in the ADV7280. The I2P block of the ADV728x works by storing a few lines of video. e.g. lines 1, 3, 5 on an odd field. It will then interpolate between these lines to generate the missing lines e.g. it will interpolate for lines 2 and 4.The I2P does contain a smoothing filter to minimize artifacts but some artifacts can still occur.
Solutions :1) Use a deinterlacer in your back end processor rather than using the I2P block of the ADV7280. The backend processor will have to store an odd frame of video in a buffer, then store an even frame of video and then switch these two frames together to generate a progressive field. This will minimize interlaced to progressive errors but will add a delay to your system.Be sure to introduce a line counter or similar software control to ensure that you do not get buffer overflows.
Does Below your solution means using another Processor? I confused it means internal or external processor.
Please clarify above question.
This thread is already marked as answered. Could you please create new thread for new questions?
That is internal processor,Please refer below attached ADV728x internal block diagram.If it is a custom one,use deinterlacer at blackened.
The front end of the ADV728x-M converts the analog video signal into an 8-bit ITU656 video stream (8 bit YCrCb 4:2:2).The 8-bit ITU656 video stream is fed into a MIPI CSI-2 Tx and D-Phy Tx, The MIPI CSI-2 Tx and D-Phy Tx serializes the video stream and outputs the video stream over a MIPI CSI-2 link. See attached diagram.Note however that the MIPI CIS-2 link remain in the 8 bit YCrCb 4:2:2 color space.Also note that the MIPI CIS-2 link retains the line and frame timing of the ITU656 specificatione.g. frame rate output is 50Hz for PAL and 60Hz for NTSC inputs, in interlaced mode odd frames have one extra line than even frames.
Unfortunately such artefacts are expected from the ADV7280.There are two possible causes of these artifacts : interlaced to progressive conversion arteiacts or 2D comb artefacts.Interlaced to progressive conversionThe I2P does contain a smoothing filter to minimise artefacts but some artefacts can still occur.2D CombThe ADV7180/ADV7182/ADV728x video decoders are designed to be low cost analog to digital video decoders and as such they only have 2D comb YC separation filters.2D comb filters are good at separating the luma and chroma information but artefacts such as the one you have highlighted are still possible. Solutions :1) Use a deinterlacer in your back end processor rather than using the I2P block of the ADV7280. The backend processor will have to store an odd frame of video in a buffer, then store an even frame of video and then stitch these two frames together to generate a progressive field. This will minimise interlaced to progressive errors but will add a delay to your system.Be sure to introduce a line counter or similar software control to ensure that you do not get buffer overflows.2) Modify some of the registers in the ADV7280 to try and minimise 2D comb this artefacts for your system. Try reading the Chroma filter, Luma Filter, Chroma Transient Improvement, Digital Noise Reduction and Luma Peaking Filter, and Comb filter sections of the ADV728x hardware manual. You may get some improvement but you will never be totally able to remove 2D comb artefacts.3) Use an Analog Devices video decoder that uses a 3D comb filter e.g. ADV7842. 3D comb will result in fewer artefacts output to the screen. However a number of frames of video need to be stored in an external SDRAM chip in order for the 3D comb filter to work. This will add a delay from inputted video to outputted video.
The Jitter may introduce due to below following reason too, If it is custom board,Please refer application note for layout design www.analog.com/.../AN-1337.pdfNote : Ensure the proper clock rate(27Mhz) has given.
All filtering and termination is performed in the D-PHY layer of the ADV7280-M,ADV7281-M, ADV7281-MA, and ADV7282-M transmitter devices and in the D-PHY layerof the MIPI CSI-2 receiver. Do not place additional components, such as resistors,electrostatic discharge (ESD) diodes, capacitors, or common-mode chokes on the MIPI CSI-2 traces And also the feedback loop between the current clamps and the video processor fine-tunes this coarse dc offset and makes the clamping robust to noise on the video input.So the current clamps are controlled within a feedback loop between the AFE and the video processor; the coarse clamps are not.