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We need "SYNC SEPARATOR" block diagrams of AD723.

Thread Summary

The user is experiencing an unstable burst signal position in CVBS output when using the AD723, due to the 4FSC running asynchronously to the RGB signal. The final answer confirms that the AD723 meets SMPTE 170M standards and refers to the datasheet for timing relationships, but the exact variation range of the burst signal start timing is not provided. The user is waiting for more detailed information from an expert.
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Hi all.

We will have to design equipment with the AD723,
Position of the burst signal of CVBS to be output is unstable.

Because 4FSC is provided only in AD723,
It is running asynchronously to the source side RGB signal.


I need an explanation on how to generate the burst signal.

Could you please provide block-diagram of the "SYNC SEPARATOR" and description of that operation mechanism?
 

 

Best Regards
aimPoint.

Parents
  • Hi GuenterL

    Thankyou quick replay.

    > The device meets SMPTE 170M standards and the datasheet shows the timing relationship between the sync pulses and the burst gate logic.
    =>
    I confirm the data sheet, but the variation range of the Burst signal start Timing is not listed numerically.


    > I'm trying to get more information from the expert to see if he can or will release more details.
    =>
    I will wait for the answer.

    Best Regards
    aimPoint.

Reply
  • Hi GuenterL

    Thankyou quick replay.

    > The device meets SMPTE 170M standards and the datasheet shows the timing relationship between the sync pulses and the burst gate logic.
    =>
    I confirm the data sheet, but the variation range of the Burst signal start Timing is not listed numerically.


    > I'm trying to get more information from the expert to see if he can or will release more details.
    =>
    I will wait for the answer.

    Best Regards
    aimPoint.

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