ADV7282 to FPGA Initialization Script

My customer is knee deep in debugging the ADV7282A/FPGA interface. It looks like he is getting bt656 data from the Adv7282A. However, the Intel FPGA CVI-II IP core is NOT resolving a valid resolution based on the data. He is using version 2.0 of the ADV7282A script from the Analog Devices webpage for the IC. He modified the script based on certain issues He found on the ADI forum that are NOT documented in the User Guide. See below:

##04_CVBS INTERLACED TO PROGRESSIVE##

        :I2P - NTSC In Ain1,YPrPb Out (480p EAV/SAV):

        delay 10ms ;

        42 0F 80 ; Reset ADV7282A

        delay 10ms ;

        42 0F 00 ; Exit Power Down Mode [ADV7282 writes begin]

        42 F4 2A ; Change drive strength to Medium high drive strength (3x)

        42 52 CD ; AFE Bias

        42 00 00 ; CVBS in on AIN1

        42 0E 80 ; ADI Required Write

        42 9C 00 ; Reset Clamp Circuitry [step1]

        42 9C FF ; Reset Clamp Circuitry [step2]

        42 0E 00 ; Enter User Sub Map

        42 80 51 ; ADI Required Write

        42 81 51 ; ADI Required Write

        42 82 68 ; ADI Required Write

        42 17 41 ; Enable SH1

        42 03 0C ; Enable Pixel & Sync output drivers

        42 04 86 ; Power-up INTRQ pad, Enable SFL & VS pin

        42 13 02 ; Enable ADV7282A for 28_63636Mhz oscillator

        42 37 00 ; Inverts the polarity of LLC(switch from P7:P0 data on negative edge to output positive edge)

        42 1D 40 ; Enable LLC output driver

        42 FD 84/94 ; Set VPP Map

        84/94 A3 00 ; ADI Required Write [ADV7282 VPP writes begin]

        84/94 5B 00 ; Enable Advanced Timing Mode

        84/94 55 80 ; Enable the Deinterlacer for I2P [All ADV7282 writes finished]

 He added a write to increase the drive strength(42 F4 2A). He changed the write to Register 0x04 since he is using an oscillator instead of a crystal (NOT documented but found on forum). He is actually using Auto-detect and Free Run. He also inverted the polarity of LLC as the FPGA core clocks data in on the negative edge of the data clock. He tried using Free Run to debug but the CVI-II core is still NOT resolving the resolution. He found, on the forum, that by default it should be 720x576i with the script settings above. However, since He setup the I2P, He should get 720x576p but He is still not getting the resolution lock in the FPGA. Is there something else He needs to do to MAKE sure that FREE RUN is running correctly? 

Mike