Problem in ADV7611 HDMI receiver with Interlace Input.

Hello folks,

We are developing demo Aplication for HDMI input and output. for this we are using PicoZed board with FMC HDMI daughter card.
the daughter card consist of Adv7611 as HDMI receiver and Adv7511 as HDMI transmitter.


when progressive input is given to Adv7611 it detects progressive input and captuers Input resolution of 1920 x 1080p.

register info:
HDMI_INTERLACED , Addr 68 (HDMI), Address 0x0B[5](Read only)
0x0B = 0x22 (detect progressive mode)

Video Input information as follow:

LineWidth =0x780  (1920)
HFrontPorch=0x58
HSyncWidth = 0x2C
HBackPorch = 0x94
HSyncPolarity = 0X01
Field0Height = 0X438  (1080)
Field1Height = 0X438
Field1TotalHeight =0X8CA
Field0TotalHeight =0x8CA
VSyncPolarity =0x01
Field1BackPorch =0x48
Field1SyncWidth =0x0A
Field0FrontPorch =0x08
Field0BackPorch =0x48

while testing with progressive input we observed that we able to see fullscreen output with 1920x1080 resolution.


***************Problem happens when input is chanaged from progressive to interlaced*******************************************

 when interlace input is given to Adv7611 it detects interlace input and captures Input resolution of 1920 x 540i instead of 1920x1080i.

HDMI_INTERLACED , Addr 68 (HDMI), Address 0x0B[5](Read only)
0x0B = 0x04 (detect interlace mode)
Video Input information as follow:

LineWidth =0x780   (1920)
HFrontPorch=0x58
HSyncWidth = 0x2C
HBackPorch = 0x94
HSyncPolarity = 0X01
Field0Height = 0X21C
Field1Height = 0X21C  (540)
Field0TotalHeight =0X466
Field1TotalHeight =0x466
VSyncPolarity =0x01
Field1BackPorch =0x1F
Field1SyncWidth =0x0A
Field0FrontPorch =0x07
Field0BackPorch =0x1E

so why does this happens?

    •  Analog Employees 
    on Apr 24, 2019 2:10 PM over 1 year ago

    Hi,

    when interlace input is given to Adv7611 it detects interlace input and captures Input resolution of 1920 x 540i instead of 1920x1080i?

      Yes.

    Generally "interlacing" was used to reduce the amount of information sent for each image. By transferring the odd-numbered lines followed by the even numbered lines as shown in below fig,the amount of information sent for each image was halved.With interlace,each scan line is refreshed half as often as it would be if it were a progressive display.
     


    Note: An interlaced display is made using two fields, each one containing one-half of the scan lines needed to make up one frame of video. Each field is displayed in its entirety—therefore, the odd field is displayed, then the even, then the odd,and so on. Fields only exist for interlaced scanning systems. So for 480i video systems, which have 525 lines per frame, a field has 262.5 lines, and two fields make up a 525-line frame.

     

    Thanks,

    Poornima

  • Thanks for such quick reply. In our case we are using input as ADV7611 and output  giving to monitor through Adv7511.

    Now our situation is when we give progressive input to Adv7611 and check on monitor,  we able to see full screen i.e. 1920 x 1080P60. 

    Test image with progressive input

    when we give interlaced input to adv7611 and check on monitor, we able to see only half screen i.e 1920x540.

    what could be possible solution to see full screen output on monitor with interlace input?

    Is it possible to see full screen output with ADV7511 having input as interlace?  If yes how to configure ADV7511 to show full screen output.

    •  Analog Employees 
    on Apr 25, 2019 7:14 AM over 1 year ago in reply to Ram09

    Hi,

     How do you configure the board either through script or software driver?

     Please refer reference script at https://ez.analog.com/video/w/documents/789/adv7611-design-support-files. Here you have all i2c related configuration in hardware/software manual.

    Thanks,

    Poornima

  • Hiii,

    We are referring same script you given.

    The Interlaced script given in the link not working properly with our system. don't know the reason?

    may be some register settings are missing.

    But the script for progressive input i.e 1920 x1080 P60 works properly with few changes. the changes are as follow.

    ADV7611 register setting:

          0x98, FF, 80 // I2C reset
          0x98, F4 ,80 //CEC
          0x98 ,F5, 6A //INFOFRAME
          0x98 ,F8, 4C // DPLL
          0x98, F9 ,64  //KSV
          0x98, FA, 6C //EDID
          0x98, FB ,68 //HDMI
          0x98, FD ,44 //CP
          0x98 , 0x00, 0x02,
          0x98 , 0x01, 0x06,
          0x98 , 0x02, 0xF5, // Auto CSC, YCrCb out, Set op_656 bit
          0x98 , 0x03, 0x80, // 16-Bit SDR ITU-R BT.656 4:2:2 Mode 0
          0x98 , 0x04, 0x62,
          0x98 , 0x05, 0x2C, // AV Codes on

          0X44, 0x7B, 0x05,
          0X44, 0xC9, 0x00,

          0x98 , 0x0B, 0x44, // Power up part
          0x98 , 0x0C, 0x42, // Power up part
          0x98 , 0x14, 0x7F, // Max Drive Strength
          0x98 , 0x15, 0x80, // Disable Tristate of Pins
          0x98 , 0x06, 0xA7, // LLC polarity (INV_LLC_POL = 1)
          0x98 , 0x19, 0x80, // LLC DLL phase (delay = 0)
          0x98 , 0x33, 0x40, // LLC DLL enable
          0x44 , 0xBA, 0x01,
          0x64, 0x40, 0x81,
          0x68 , 0x4C, 0x44,
          0x68 , 0x9B, 0x03, // ADI recommended setting
          0x68 , 0xC1, 0x01, // ADI recommended setting
          0x68 , 0xC2, 0x01, // ADI recommended setting
          0x68 , 0xC3, 0x01, // ADI recommended setting
          0x68 , 0xC4, 0x01, // ADI recommended setting
          0x68 , 0xC5, 0x01, // ADI recommended setting
          0x68 , 0xC6, 0x01, // ADI recommended setting
          0x68 , 0xC7, 0x01, // ADI recommended setting
          0x68 , 0xC8, 0x01, // ADI recommended setting
          0x68 , 0xC9, 0x01, // ADI recommended setting
          0x68 , 0xCA, 0x01, // ADI recommended setting
          0x68 , 0xCB, 0x01, // ADI recommended setting
          0x68 , 0xCC, 0x01, // ADI recommended setting
          0x68 , 0x00, 0x00,
          0x68 , 0x02, 0x03,
          0x68 , 0x83, 0xFC,
          0x68 , 0x6F, 0x0C, // ADI recommended setting
          0x68 , 0x85, 0x1F, // ADI recommended setting
          0x68 , 0x87, 0x70, // ADI recommended setting
          0x68 , 0x8D, 0x04, // LFG Port A
          0x68 , 0x8E, 0x1E, // HFG Port A
          0x68 , 0x1A, 0x8A, // Unmute audio
          0x68 , 0x57, 0xDA, // ADI recommended setting
          0x68 , 0x58, 0x01, // ADI recommended setting
          0x68 , 0x75, 0x10, // DDC drive strength
          0x68 , 0x90, 0x04, // LFG Port B
          0x68 , 0x91, 0x1E,  // HFG Port B
          0x68 , 0x98, 0x03
          0X68, 0x03, 0x78, // Raw SPDIF Mode
          0x68, 0x6E, 0x0C

    ADV7511 register setting:

          0x72, 0x01, 0x00, // Set N Value = 6144 (0x001800) for 48 kHz
          0x72, 0x02, 0x18,
          0x72, 0x03, 0x00,
          0x72, 0x0A, 0x10,
          0x72, 0x0B, 0x8E,
          0x72, 0x0C, 0x00,
          0x72, 0x73, 0x01,
          0x72, 0x14, 0x02,
          0x72, 0x15, 0x02, // Input YCbCr 4:2:2 with embedded syncs
          0x72, 0x16, 0x38,
          0x72, 0x17, 0x02,
          0x72, 0x18, 0xC6,
          0x72, 0x40, 0x80, // General Control packet enable
          0x72, 0x48, 0x10,
          0x72, 0x49, 0xA8, // Bit trimming mode = 101010 (truncate)
          0x72, 0x4C, 0x00, // Color Depth = 0000 (color depth not indicated)
          0x72, 0x55, 0x00,
          0x72, 0x56, 0x08,


          0x72, 0xAF, 0x16,
          0x72, 0x98, 0x03, // ADI Recommended Write
          0x72, 0x99, 0x02, // ADI Recommended Write
          0x72, 0x9A, 0xE0, // ADI Recommended Write
          0x72, 0x9C, 0x30, // PLL Filter R1 Value
          0x72, 0x9D, 0x61, // Set clock divide
          0x72, 0xA2, 0xA4, // ADI Recommended Write
          0x72, 0xA3, 0xA4, // ADI Recommended Write
          0x72, 0xA5, 0x44, // ADI Recommended Write
          0x72, 0xAB, 0x40, // ADI Recommended Write
          0x72, 0xBA, 0xA0, // Programmable delay for input video clock = 101 = +0.8ns
          0x72, 0xD0, 0x00, // Delay adjust for negative DDR capture = disabled
          0x72, 0xD1, 0xFF, // ADI Recommended Write
          0x72, 0xDE, 0x9C, // ADI Recommended Write
          0x72, 0xE0, 0xD0, // ADI Recommended Write
          0x72, 0xE4, 0x60, // VCO_Swing_Reference_Voltage
          0x72, 0xF9, 0x00,

     Configure for 1080p60 16-bit bus embedded syncs
      
       0x72, 0x30, 0x16, // Hsync placement = 0001011000 (0x58) = 88
       0x72, 0x31, 0x02, // Hsync duration  = 0000101100 (0x2C) = 44
       0x72, 0x32, 0xC0, //
       0x72, 0x33, 0x10, // Vsync placement = 0000000100 (0x04) =  4
       0x72, 0x34, 0x05, // Vsync duration  = 0000000101 (0x05) =  5
       0x72, 0x17, 0x00  // VSync Polarity = 0(high), HSync Polarity = 0(high)

    •  Analog Employees 
    on Apr 26, 2019 6:51 AM over 1 year ago in reply to Ram09

    Hi,

    Please crosscheck with below two register,

    CP_FORCE_INTERLACED, IO, Address 0x12[1] (Read Only)
         This readback to indicate forced-interlaced status of the CP core based on configuration of video standard and INTERLACED bit in the cp map.



    INTERLACED -Address 44 (CP), Address 0x91[6]
        By default it will be in interlaced video mode.If not, sets the interlaced/progressive mode of the incoming video processed in CP mode.

     

    Thanks,

    Poornima.S