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SHARC 21369 SPORT I2S, Left Justified limitation?

Question asked by Tyrone on Nov 4, 2011
Latest reply on Jan 24, 2012 by DeepV

Hi All,

 

I was working on a project that allow user to change the signal pattern of the received serial signal with

1. Bit Clock Polarity

2. Frame Clock Polarity

 

Looking at the HRM I figure to receive a I2S signal / Left justified signal in the following configuration is imposible

 

1. Bit Clock Falling Edge Sample (Data line sample at falling edge)

 

Due to the fact the CKRE bit in SPORT is reserved while the OPMODE has been set.

 

I have tried a few work around by toying with various setting of DSP mode (OPMODE = 0) which fail to receive the I2S/Left justify signal at proper alignment.

 

Anyone face the same issue?

 

Left Justified emulated setting with (OPMODE = 0)

 

SAUD_WL = 32;

SAUD_FCLK = FSR;

SAUD_SCLK = CKRE; (Rising edge sample)

 

 

*pSPCTL2 = ( SAUD_WL | SPEN_A | SCHEN_A | SDEN_A|SAUD_FCLK | SAUD_SCLK | LAFS );

 

I2S emulated setting with (OPMODE = 0)

 

SAUD_WL = 32;

SAUD_FCLK = FSR;

SAUD_SCLK = CKRE; (Rising edge sample)

 

 

*pSPCTL2 = ( SAUD_WL | SPEN_A | SCHEN_A | SDEN_A|SAUD_FCLK | SAUD_SCLK );

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