I am currently working with the AD9637-80EBZ evaluation kit in conjunction with the HSC-ADC-EVALCZ evaluation kit. for the ADC value readout I use the Visual Analog software and the ADC's SPI interface is controlled by the SPI Controller from AD. A 20Mhz clock is supplied to the AD9637-80EBZ evaluation kit and J804 is removed. The binary file inside the Virtex-4 FPGA on the HSC-ADC-EVALCZ evaluation kit is Octal_Low_Speed.bin because sample-rate < 30Msps. When the input formatter in the Visual Analog software is set to 2's complement (Resolution: 12 and Alignment 12) and the ADC is configured to output the data in 2's complement mode everything works fine. If I change the ADC output mode setting (register 0x14) to offset binary mode everything still works fine while the data that is transmitted to the Visual Analog software has a different format (not 2's complement). When I change the input formatter from 2's complement to offset binary things start to get worse even more. What I see on the graph is the binary representation of 2's complement values.
Is there a possibility that the FPGA / Visual analog software knows in which format the incoming data is formatted? Also when the SPI register is changed?