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AD7761 Throughput and Dclk

Question asked by EngJunkie on Oct 17, 2017
Latest reply on Oct 20, 2017 by EngJunkie

Hey everyone,


I have a quick question on the Dclk of the AD7761,On page 45 of the datasheet, It states the minimum Dclk configuration that can be used is dependent on the throughput and channels per Doutx.


I'll be using a daisy chain configuration of three devices (so 2 output lines) and I plan on having a dataoutput rate of 16Khz ( as defined in table 10/11 on page 28).


So my minimum Dclk should be = 16ksPs * 2 channels * 24 = 768 kHz, but it seems the Dclk division can only be a minimum of Mclk/8 and Mclk needs to be 32.768 Mhz, so this equates to 4.096 MHz, which is a lot higher than my required Dclk. Is there any way that I can get the Dclk closer to 800 kHz? It'll be easier on my processor to process the incoming data if it comes out close to 800 kHz instead of 4MHz


Thanks in advance for any help.