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ADV7180 Artifact

Question asked by FrancoisLegal on Oct 17, 2017
Latest reply on Oct 19, 2017 by FrancoisLegal

Hello,

 

using an FPGA to acquire Y data from an ADV7180 ADC, I'm facing a weird problem.

 

When I display the sampled data, I have random grey lines on the screen. By searching on my design, I could see that once in a while, my sampling on the digital side, switch "one LLC cycle" and sample Cb & Cr bytes instead of Y bytes.

 

By checking the signals on the board, I could see that sometimes, the LLC signal has almost a half period jitter. I could read that LLC can have +/- 5% jitter, half a period is a lot over that specification. What could be the cause of this problem ?

 

Thanks in advance.

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