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ad9361 LVDS data_clk

Question asked by buzuoluren on Oct 17, 2017
Latest reply on Oct 19, 2017 by Vinod


I got some problems when debugging AD9361 receiving, I chose the LVDS, DDR data interface, the interface rate is set to 60M, clock_out set to 60M. In the debugging use of the spectrum analyzer, I got data_clk_p is 120M, clock_out is 60M, is it in normal circumstances?