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AD9361 DATA_CLK is unstable

Question asked by 科大小生 on Oct 17, 2017
Latest reply on Oct 19, 2017 by Vinod

I now in TDD mode, the configuration of the 1R1T mode, the launch part of the normal work, DATA_CLK can be stable, but I switch the state machine to switch to RX state, DATA_CLK becomes very unstable, and then switch to TX state, DATA_CLK It is not stable, which led to I can not receive the signal, do not know where the problem is, I was designing their own circuit diagram, but I are based on AD9361 configuration software to write the register value, but also according to the order To write the register value, I am now worried about the RX channel calibration is not set up correctly, this problem has been confused for a long time, ask your friends to help explain it

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