I modify the reference design by adding a regional buffer (BUFR) in front of the mmcm of DDS core.
And I set the parameter BUFR_DIVIDE 4 to reduce the input clock frequency 4 times. And in SDK, I change the parent_rate in function mmcm_set_rate into 1/4 times to match my PL modification. But the result is wrong.
What should I do more in SDK or vivado to get the correct result?