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FMCOMMS2 support for A10GX?

Question asked by EthanChen on Oct 13, 2017
Latest reply on Oct 23, 2017 by rgetz

Hello,

 

I previously used Ad9361 with A10GX and A10SOC, but It failed.

 

I used branch of hdl_2016_r2 from GitHub - analogdevicesinc/hdl: HDL libraries and projects and tools of  Quartus Prime 16.0 Standard Edition. When I was building the hardward design using the command 'source ./system_project.tcl' on the Quartus Tcl Console, it showed up some error messages listed below

 

Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_0"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_1"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_2"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_3"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_4"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_5"
Error (12004): Port "clock0" does not exist in primitive "stratixii_lvds_transmitter" of instance "tx_6"
Error (12152): Can't elaborate user hierarchy "system_bd:i_system_bd|axi_ad9361:axi_ad9361|axi_ad9361_lvds_if:i_dev_if|axi_ad9361_alt_lvds_tx:i_tx|altlvds_tx:i_altlvds_tx|axi_ad9361_alt_lvds_tx_lvds_tx:auto_generated"
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 44 warnings
Error: Peak virtual memory: 1038 megabytes
Error: Processing ended: Fri Oct 13 11:45:00 2017
Error: Elapsed time: 00:01:01
Error: Total CPU time (on all processors): 00:01:35
Error (293001): Quartus Prime Full Compilation was unsuccessful. 10 errors, 44 warnings

 

I found some information at Releases · analogdevicesinc/hdl · GitHub about 

'

  • The FMCOMMS2 projects on Arria 10 devices is provided as a template ONLY. The project will NOT work on hardware (A10GX or A10SOC) due to Altera's lack of knowledge on their device bank/FMC pin assignments.

'

And I Searched related issues listed below

  Altera SoC support for AD9361,

  Is there a plan to release hdl project supporting Arria10SoC/AD9361?,

  Ad9361 interface to altera,

  AD-FMComms2 HDL support for Altera FPGAs

 

How can I fix it?

Is there more information or are there materials available which can help me compile the project for FMCOMMS2 + A10GX or FMCOMMS2 + A10SOC ?

 

Many thanks,

Ethan

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