AnsweredAssumed Answered

About AD9361 BBPLL

Question asked by buzuoluren on Oct 12, 2017
Latest reply on Oct 23, 2017 by sripad

When the configuration is initialized, the BBPLL and ADC sampling clocks are set like this:
SPIWrite 045,00 //
SPIWrite 046,06 //
SPIWrite 048,E8//
SPIWrite 049,5B //
SPIWrite 04A,35 //
SPIWrite 04B,E0 //
SPIWrite 04E,10 //
SPIWrite 043,00 //
SPIWrite 042,00 //
SPIWrite 041,00 //
SPIWrite 044,20 //
SPIWrite 03F,05 //
SPIWrite 03F,01 //
SPIWrite 04C,86//
SPIWrite 04D,01 //
SPIWrite 04D,05 //
WAIT_CALDONE BBPLL,2000

SPIRead 05E

SPIWrite 002,9D //
SPIWrite 003,9D //
SPIWrite 004,03 //
SPIWrite 00A,34 //

I would like to let BBPLL= 1280M, clk_out = 40M, ADC clock = 80M, data_clk = 10M, but the configuration of the results obtained after the test is clk_out = 40M, data_clk = 40M, consulting where the problem lies?

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