I'm using the AD9208-EBZ evaluation board to obtain a high-speed ADC capture, roughly following the evaluation guide, but with the difference that I'm using an FPGA (zynq ultrascale+) instead of the ADS7-V2.
When looking at the schematic for the evaluation board, it seems that the reference clock input (J3) is only connected to FMC-pins G6 and G7. There is also a label attached to FMC-locations D4 and D5, but on inspecting the schematic, they seem to be unconnected.
Unfortunately, locations D4 and D5 are connected to the gigabit-transceiver reference clock pins on my FPGA board, while locations G6 and G7 are only routed to clock-capable IO pins. This seems to be reflected in the labels on the FMC connector.
My questions are:
- Is it correct that FMC pins D4 and D5 (labeled EXT_REFCLK_TO_FPGA+/-) are unconnected on the evaluation board and it is not possible to get the reference clock on these pins?
- If this is indeed not possible, it seems to be far from trivial to route the clock to the correct location on FPGA. The GT's need their clock input from a IBUFDS_GTHE4, but this is not available in the IO-bank where the reference clock comes in. Do you have any sample FPGA-code, for example the one used in the ADS7-V2 ,which we could inspect to find out how to get the clock to the gigabit-transceivers?