I was wondering whether someone has already tried to drive the (E)PPI to the limits.
The HRM say: PPI_CLK must be lower than SCLK/2. So far so good. This means, for a 133 MHz SCLK limited by SDRAM speed, the theoretical limit would be 66 MHz. However, I have observed, that - at least under a complex OS - the practical limit is more around 40 MHz due to FIFO overflows on heavy bus load, because program data and image data is transferred from/to SDRAM.
On the BF54x series, I'd expect a higher total system bandwidth due to DDR RAM, but the SCLK limit is still the same.
Last scenario: If no SDRAM would be used, what would the practical limit be like, when just using PPI -> SRAM *> SRAM -> Output
'->' be a DMA transfer, '*>' some CPU processing